Haruhiko Ono

Interfacial reactions between thin rare-earth-metal oxide films and Si substrates

Rare-earth-metal oxide films (Ln2O3; Ln=Y, La, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Er, Tm, and Yb) between 20 and 30 nm thick were grown on Si substrates by using a pyrolysis method. We found that a silicate (LnSiO) layer and a silicon oxide layer were formed at the interface between oxides and substrate after postannealing. The infrared absorption of the Si–O–Ln bonds increased as the postannealing temperature rose. The Si–O–Ln bond formation strongly depended on the ion radii of the rare-earth elements. We conclude that an interfacial silicate layer can easily be formed by a reaction with Si atoms diffusing from the substrate for oxides with larger ion radii. This is because such oxides may have a larger space between atoms. The quantity of Si–O–Si bonds also increased after postannealing. The increase in the Si–O–Si bonds for Ln2O3 was independent of the elements, and almost the same as the increases for Ta2O5 and ZrO2.

Effects of thermal annealing on porous silicon photoluminescence dynamics

Photoluminescence (PL) spectra and decay dynamics were studied for the spontaneously oxidized porous Si with subsequent various thermal annealing procedures. The PL decay was highly nonexponential and well described by the stretched‐exponential function. The PL lifetime was shorter for the higher PL photon energy, but at the same photon energy it decreased by an order of magnitude by the thermal annealing in N2 gas, in parallel with the large PL intensity decrease. This PL quenching upon the annealing is presumably ascribable to both the structural changes and dangling bond formations in porous Si, as suggested by ESR measurements and the annealing experiments in H2 gas.

RuO2/TiN-based storage electrodes for (Ba, Sr)TiO3 dynamic random access memory capacitors

Sputtered (Ba, Sr)TiO 3 (BST) thin film capacitors have been fabricated with thick RuO 2 /TiN-based storage electrodes and poly-Si contact plugs, and the electrical properties of the storage electrodes have been studied. The electrode height was higher than 450 nm and the contact size was 0.8 x 0.8 μm 2 . Resistance of the storage electrodes including contact plugs can be evaluated from the dispersion observed in capacitance-frequency measurements. TiN oxidation at the RuO 2 /TiN interface and native oxide at the TiN/Si contact contribute to the electrode resistance of RuO 2 /TiN electrodes. With increasing BST deposition temperature, the thickness of oxidized TiN in RuO 2 /TiN electrbdes increases and the electrode resistance increases correspondingly. A Ru layer inserted at the RuO 2 /TiN interface, a TiN/TiSi 2 /Si junction and rapid thermal annealing in N 2 ambient of the TiN layer are effective ways to reduce the resistance of RuO 2 /TiN-based electrodes.

Infrared absorption peak due to Ta=O bonds in Ta2O5 thin films

Ta2O5 films deposited on Si substrates were investigated using transmission Fourier-transform infrared spectroscopy. We found a new absorption peak at 2340 cm−1 that can be characterized as a stretching vibration mode due to Ta=O bonds in the films. This peak appeared following annealing in O2 ambient, but not in N2 ambient. It was located at 2335 cm−1 in amorphous Ta2O5 films and shifted to 2340 cm−1 after crystallization by annealing at over 700 °C. The bonds associated with the peak were homogeneously distributed in the film. We demonstrated that Ta2O5 films can include strong double bonds between Ta and O (Ta=O) in the structure, independent of whether they are crystalline or amorphous.

Infrared studies of transition layers at SiO2/Si interface

We investigated transition layers at the interface of the thin SiO2 film successively etched back by diluted HF, using infrared reflection-absorption spectroscopy. The etching rate of the oxide film reveals that there is a Si-rich transition layer within 0.6 nm of the interface. However, frequency shift in the longitudinal optical phonon due to Si-O-Si asymmetric stretching toward lower wave numbers takes place less than 1.5 nm from the interface. We propose a model in which the transition layer is assumed to be Si-rich suboxide layers caused by the compositional roughness of the SiO2/Si interface. Through estimating the phonon frequencies which depend on the composition of the suboxide structure in this model, we found that the phonon frequency apparently starts to shift at around 1.5 nm from the interface, even if there are suboxide-rich layers within 0.6 nm, which can be caused by 1–2 monolayers of roughness.

Hemispherical grained Si formation on in-situ phosphorus doped amorphous-Si electrode for 256 Mb DRAM's capacitor

The cylindrical capacitor structure with hemispherical grained-Si (HSG-Si) described here reliably achieves a cell capacitance of 30 fF in a 0.4 /spl mu/m-high storage electrode with a cell area of a 0.72 /spl mu/m/sup 2/ for 256 Mbit dynamic random access memory. An HSG-Si formation technology using Si/sub 2/H/sub 6/-molecule irradiation and annealing enables control of the grain density and grain size of HSG-Si fabricated selectively on the whole surface of phosphorus-doped amorphous Si cylindrical electrodes. >

A stacked capacitor technology with ECR plasma MOCVD (Ba,Sr)TiO/sub 3/ and RuO/sub 2//Ru/TiN/TiSi/sub x/ storage nodes for Gb-scale DRAMs

A Gb-scale DRAM stacked capacitor technology with (Ba,Sr)TiO/sub 3/ thin films is described, The four-layer RuO/sub 2//Ru/TiN/TiSi/sub x/, storage node configuration allows 500/spl deg/C processing and fine-patterning down to the 0.20 /spl mu/m size by electron beam lithography and reactive ion etching. Good insulating (Ba/sub 0.4/Sr/sub 0.6/)TiO/sub 3/ (BST) films with an SiO/sub 2/ equivalent thickness of 0.65 nm on the electrode sidewalls and leakage current of 1/spl times/10/sup -/6 A/cm/sup 2/ at 1 V are obtained by ECR plasma MOCVD without any post-deposition annealing, A lateral step coverage of 50% for BST is observed on the 0.2 /spl mu/m size storage node pattern, and the BST thickness on the sidewalls is very uniform, thanks to the ECR downflow plasma. Using this stacked capacitor technology, a sufficient cell capacitance of 25 fF for 1 Gb DRAMs can be achieved in a capacitor area of 0.125 /spl mu/m/sup 2/ with only the 0.3 /spl mu/m high-storage electrodes.

Crystallization of Amorphous Silicon with Clean Surfaces

Crystallization of amorphous Si (a-Si) on SiO2 layers in ultra-high vacuum (UHV) was examined by transmission electron microscopy (TEM) and reflection high energy electron diffraction. The SiO2 growth, the a-Si deposition on the SiO2 layer, and the annealing for the crystallization were successively carried out in a UHV molecular-beam-epitaxy chamber. It has been found that the initial nucleation and the grain growth occur at the surface of the a-Si layer, in contrast with the nucleation at the a-Si/SiO2 interface ordinarily observed in the previous studies. Cross-sectional TEM observations revealed a novel mode of crystallization which resulted in the formation of mushroom-shaped Si grains at the a-Si surface. The mechanism of the crystallization was also discussed.

SrTiO3 thin films by mocvd for 1 gbit DRAM application

Abstract Three important aspects of the preparation of SrTiO3 thin films by MOCVD are discussed in detail in view of the application of these films as the capacitor dielectric of Gbit-scale DRAMs: CVD reactions in the Sr(DPM)2-Ti(i-OC3H7)4-O2 system, step coverage and relations between microstructure and electrical properties. The effect of the substrate temperature on the Sr and Ti deposition rates was first investigated for thermal and ECR CVD SrTiO3 films. SrO and TiO2 deposition by thermal CVD above 550°C were found to be controlled by the surface reaction and gas transport, respectively, whereas both SrO and TiO2 deposition are controlled by gas transport for ECR CVD at 450 to 600°C. The influence of the Sr and Ti deposition regimes on the step coverage of SrO, TiO2 and SrTiO3 were then assessed. SrO films prepared by thermal CVD at 600°C exhibited the best step coverage, indicating that a relation exists between reaction controlled deposition and good step coverage. The effect of the film compositio...

Formation of silicon–oxide layers at the interface between tantalum oxide and silicon substrate

Silicon–oxide layers formed at the tantalum–oxide/silicon interface were investigated by using Fourier transform infrared spectroscopy (FTIR). The samples were annealed in oxygen atmosphere, in nitrogen atmosphere, and in vacuum. It has been found that the formation of the interfacial silicon–oxide layers depends neither on the tantalum–oxide thickness nor on the annealing atmosphere, but on the annealing temperature. The silicon–oxide layer is formed even by annealing in vacuum. It is concluded that the silicon–oxide layer is formed not by a diffusion of the oxygen from the annealing atmosphere, but by a reaction between the tantalum–oxide film and the Si substrate. FTIR analysis and transmission electron microscopy of the interfacial layer show that the silicon–oxide layer has a bonding configuration different from a pure silicon dioxide.