Angelique Raley

Self-aligned quadruple patterning integration using spacer on spacer pitch splitting at the resist level for sub-32nm pitch applications

Multiple patterning integrations for sub 193nm lithographic resolution are becoming increasingly creative in pursuit of cost reduction and achieving desired critical dimension. Implementing these schemes into production can be a challenge. Aimed at reducing cost associated with multiple patterning for the 10nm node and beyond, we will present a self-aligned quadruple patterning strategy which uses 193nm immersion lithography resist pattern as a first mandrel and a spacer on spacer integration to enable a final pitch of 30nm. This option could be implemented for front end or back end critical layers such as Fin and Mx. Investigation of combinations of low temperature ALD films such as TiO, Al2O3 and SiO2 will be reviewed to determine the best candidates to meet the required selectivities, LER/LWR and CDs.

Challenges and mitigation strategies for resist trim etch in resist-mandrel based SAQP integration scheme

Patterning the desired narrow pitch at 10nm technology node and beyond, necessitates employment of either extreme ultra violet (EUV) lithography or multi-patterning solutions based on 193nm-immersion lithography. With enormous challenges being faced in getting EUV lithography ready for production, multi-patterning solutions that leverage the already installed base of 193nm-immersion-lithography are poised to become the industry norm for 10 and 7nm technology nodes. For patterning sub-40nm pitch line/space features, self-aligned quadruple patterning (SAQP) with resist pattern as the first mandrel shows significant cost as well as design benefit, as compared to EUV lithography or other multi-patterning techniques. One of the most critical steps in this patterning scheme is the resist mandrel definition step which involves trimming / reformation of resist profile via plasma etch for achieving appropriate pitch after the final pattern. Being the first mandrel, the requirements for the Line Edge Roughness (LER) / Line Width Roughness (LWR); critical dimension uniformity (CDU); and profile in 3-dimensions for the resist trim / reformation etch is extremely aggressive. In this paper we highlight the unique challenges associated in developing resist trim / reformation plasma etch process for SAQP integration scheme and summarize our efforts in optimizing the trim etch chemistries, process steps and plasma etch parameters for meeting the mandrel definition targets. Finally, we have shown successful patterning of 30nm pitch patterns via the resist-mandrel SAQP scheme and its implementation for Si-fin formation at 7nm node.

EPE improvement thru self-alignment via multi-color material integration

As the industry marches on onto the 5nm node and beyond, scaling has slowed down, with all major IDMs & foundries predicting a 3-4 year cadence for scaling. A major reason for this slowdown is not the technical challenge of making features smaller, but effective control of variation that creeps in to the fabrication process. That variability manifests itself as edge placement error (EPE), which has a direct impact on wafer yield. Simply defined as the variance between design intent vs. actual on-wafer results, EPE is one of the foremost challenges being faced by the industry at the advanced node for both logic and memory. This is especially critical at three stages: the front end of line (FEOL) STI patterning; middle of line (MOL) contact patterning; and back end of line (BEOL) trench patterning where the desired tight pitch demands EPE control beyond the capability of 193i multi-patterning or even EUV single pattern. In order to mitigate this EPE challenge, we are proposing self-alignment of blocks & cuts through a multi-color materials integration concept. This approach, termed as “Self-aligned block or Cut (SAB or SACut)”, simply trades off the un-manageable overlay requirement into a more manageable etch selectivity challenge, by having multiple materials filled in every other trench or line. In this paper we will introduce self-alignment based block and cut strategies using multi-color materials integration and show implementation for BEOL trench block patterning. We will present a breakdown of the key unit process challenges that were needed to be resolved for enabling the self-alignment such as: (a) material selection of multi-color approach; (b) planarization of spin on materials; (c) void-free gap fill for high aspect ratio features; and last but not the least, (c) etch selectivity of etching one material with respect to all other materials exposed. Further, we will present a comparison of our new self-alignment approach with standard approaches where we will articulate the advantages in terms of EPE relaxation and mask number reduction. We will conclude our talk with a brief snapshot of the future direction of our EPE improvement strategies and our view on the future of patterning beyond 5nm node for the industry.

Multi-color fly-cut-SAQP for reduced process variation

Multi-patterning processes such as self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) present new challenges to the semiconductor device manufacturing such as increased relative cost to previous nodes, longer cycle times, and increased (local) edge placement error between grid and cut/block layers. As the scaling requirements continue, the factors driving both EPE and electrical yield such as overlay, critical dimension control (CDU) and stochastics (LCDU) become greater concerns to multi-patterning. In addition to lithographic process variations, the unit processes such as plasma/vapor etch, deposition, wet/cleans can contributes additional variation in spacer/mandrel profiles leading to poor CDU control and ultimately within-wafer pitch walking. In this paper, we outline alternative SAQP integration schemes to improve the feature profile of both mandrel and spacer to minimize process variability. This patterning scheme designated as fly-cut SAQP introduces new concepts such top spacer removal by chemical-mechanical planarization, mandrel foot mitigation layers, multi-layered mandrel for accurate polish end-point and void-free gap fill to realize high fidelity transfer to the underlying hardmask. Finally, we will demonstrate the effectiveness for this new integration scheme as a candidate for multi-color/self-aligned block (SAB) and highlight the additional benefits of using such an approach.

Self-aligned blocking integration demonstration for critical sub-30nm pitch Mx level patterning with EUV self-aligned double patterning

We report a sub-30nm pitch self-aligned double patterning (SADP) integration scheme with EUV lithography coupled with self-aligned block technology (SAB) targeting the back end of line (BEOL) metal line patterning applications for logic nodes beyond 5nm. The integration demonstration is a validation of the scalability of a previously reported flow, which used 193nm immersion SADP targeting a 40nm pitch with the same material sets (Si3N4 mandrel, SiO2 spacer, Spin on carbon, spin on glass). The multi-color integration approach is successfully demonstrated and provides a valuable method to address overlay concerns and more generally edge placement error (EPE) as a whole for advanced process nodes. Unbiased LER/LWR analysis comparison between EUV SADP and 193nm immersion SADP shows that both integrations follow the same trend throughout the process steps. While EUV SADP shows increased LER after mandrel pull, metal hardmask open and dielectric etch compared to 193nm immersion SADP, the final process performance is matched in terms of LWR (1.08nm 3 sigma unbiased) and is only 6% higher than 193nm immersion SADP for average unbiased LER. Using EUV SADP enables almost doubling the line density while keeping most of the remaining processes and films unchanged, and provides a compelling alternative to other multipatterning integrations, which present their own sets of challenges.

EUV patterning using CAR or MOX photoresist at low dose exposure for sub 36nm pitch

The semiconductor industry has been pushing the limits of scalability by combining 193nm immersion lithography with multi-patterning techniques for several years. Those integrations have been declined in a wide variety of options to lower their cost but retain their inherent variability and process complexity. EUV lithography offers a much desired path that allows for direct print of line and space at 36nm pitch and below and effectively addresses issues like cycle time, intra-level overlay and mask count costs associated with multi-patterning. However it also brings its own sets of challenges. One of the major barrier to high volume manufacturing implementation has been hitting the 250W power exposure required for adequate throughput [1]. Enabling patterning using a lower dose resist could help move us closer to the HVM throughput targets assuming required performance for roughness and pattern transfer can be met. As plasma etching is known to reduce line edge roughness on 193nm lithography printed features [2], we investigate in this paper the level of roughness that can be achieved on EUV photoresist exposed at a lower dose through etch process optimization into a typical back end of line film stack. We will study 16nm lines printed at 32 and 34nm pitch. MOX and CAR photoresist performance will be compared. We will review step by step etch chemistry development to reach adequate selectivity and roughness reduction to successfully pattern the target layer.

Self-aligned quadruple patterning using spacer on spacer integration optimization for N5

To meet scaling requirements, the semiconductor industry has extended 193nm immersion lithography beyond its minimum pitch limitation using multiple patterning schemes such as self-aligned double patterning, self-aligned quadruple patterning and litho-etch / litho etch iterations. Those techniques have been declined in numerous options in the last few years. Spacer on spacer pitch splitting integration has been proven to show multiple advantages compared to conventional pitch splitting approach. Reducing the number of pattern transfer steps associated with sacrificial layers resulted in significant decrease of cost and an overall simplification of the double pitch split technique. While demonstrating attractive aspects, SAQP spacer on spacer flow brings challenges of its own. Namely, material set selections and etch chemistry development for adequate selectivities, mandrel shape and spacer shape engineering to improve edge placement error (EPE). In this paper we follow up and extend upon our previous learning and proceed into more details on the robustness of the integration in regards to final pattern transfer and full wafer critical dimension uniformity. Furthermore, since the number of intermediate steps is reduced, one will expect improved uniformity and pitch walking control. This assertion will be verified through a thorough pitch walking analysis.

Dry-plasma-free chemical etch technique for variability reduction in multi-patterning (Conference Presentation)

Scaling beyond the 7nm technology node demands significant control over the variability down to a few angstroms, in order to achieve reasonable yield. For example, to meet the current scaling targets it is highly desirable to achieve sub 30nm pitch line/space features at back-end of the line (BEOL) or front end of line (FEOL); uniform and precise contact/hole patterning at middle of line (MOL). One of the quintessential requirements for such precise and possibly self-aligned patterning strategies is superior etch selectivity between the target films while other masks/films are exposed. The need to achieve high etch selectivity becomes more evident for unit process development at MOL and BEOL, as a result of low density films choices (compared to FEOL film choices) due to lower temperature budget. Low etch selectivity with conventional plasma and wet chemical etch techniques, causes significant gouging (un-intended etching of etch stop layer, as shown in Fig 1), high line edge roughness (LER)/line width roughness (LWR), non-uniformity, etc. In certain circumstances this may lead to added downstream process stochastics. Furthermore, conventional plasma etches may also have the added disadvantage of plasma VUV damage and corner rounding (Fig. 1). Finally, the above mentioned factors can potentially compromise edge placement error (EPE) and/or yield. Therefore a process flow enabled with extremely high selective etches inherent to film properties and/or etch chemistries is a significant advantage. To improve this etch selectivity for certain etch steps during a process flow, we have to implement alternate highly selective, plasma free techniques in conjunction with conventional plasma etches (Fig 2.). In this article, we will present our plasma free, chemical gas phase etch technique using chemistries that have high selectivity towards a spectrum of films owing to the reaction mechanism ( as shown Fig 1). Gas phase etches also help eliminate plasma damage to the features during the etch process. Herein we will also demonstrate a test case on how a combination or plasma assisted and plasma free etch techniques has the potential to improve process performance of a 193nm immersion based self aligned quandruple patterning (SAQP) for BEOL compliant films (an example shown in Fig 2). In addition, we will also present on the application of gas etches for (1) profile improvement, (2) selective mandrel pull (3) critical dimension trim of mandrels, with an analysis of advantages over conventional techniques in terms of LER and EPE.

Self-aligned blocking integration demonstration for critical sub-40nm pitch Mx level patterning

Multipatterning has enabled continued scaling of chip technology at the 28nm node and beyond. Selfaligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) as well as Litho- Etch/Litho-Etch (LELE) iterations are widely used in the semiconductor industry to enable patterning at sub 193 immersion lithography resolutions for layers such as FIN, Gate and critical Metal lines. Multipatterning requires the use of multiple masks which is costly and increases process complexity as well as edge placement error variation driven mostly by overlay. To mitigate the strict overlay requirements for advanced technology nodes (7nm and below), a self-aligned blocking integration is desirable. This integration trades off the overlay requirement for an etch selectivity requirement and enables the cut mask overlay tolerance to be relaxed from half pitch to three times half pitch. Selfalignement has become the latest trend to enable scaling and self-aligned integrations are being pursued and investigated for various critical layers such as contact, via, metal patterning. In this paper we propose and demonstrate a low cost flexible self-aligned blocking strategy for critical metal layer patterning for 7nm and beyond from mask assembly to low –K dielectric etch. The integration is based on a 40nm pitch SADP flow with 2 cut masks compatible with either cut or block integration and employs dielectric films widely used in the back end of the line. As a consequence this approach is compatible with traditional etch, deposition and cleans tools that are optimized for dielectric etches. We will review the critical steps and selectivities required to enable this integration along with bench-marking of each integration option (cut vs. block).

A spacer-on-spacer scheme for self-aligned multiple patterning and integration

To enable lithographic printing of ever smaller features, multipatterning techniques are increasingly being used in the semiconductor industry. These techniques are designed to extend 193nm immersion lithography, which is necessary to enable designs at 20nm or below. Multipatterning methods, however, are typically two to three times more expensive for each wafer than for a theoretical 193nm-immersion-based single exposure (assuming that 193nm immersion could be used to achieve the desired pitch). Moreover, extreme UV (EUV) lithography—a technology for the 5nm node that is expected to be available after 2020—is a costly option for high-volume production at major foundries and integrated device manufacturers (see Figure 1).1 At present, self-aligned quadruple patterning (SAQP) is the optimum technique for patterning of layers that require the most aggressive pitch shrink (such as fin formation and critical metal layers). In a standard SAQP stack, two hard mandrels are used alongside the appropriate etch stop and hardmask layers (see Figure 2). Integration of these components, however, is complex and involves several sacrificial layers that require multiple dry-etch and wet-etch steps. In response to this complexity, developers have so far made several attempts to simplify multipatterning processes, and to reduce costs and improve throughput.2, 3 We propose a low-cost alternative SAQP scheme that features no sacrificial layers, and which uses a spacer-on-spacer pitch-splitting strategy (see Figure 3). With our method, which requires careful selection of the underlying substrate, mandrel, and spacer materials, we can achieve a 25% reduction in cost Figure 1. Normalized wafer cost adder for different multipatterning techniques, according to internal TEL calculations. Numbers in the right hand column are multiples of the cost of single exposure patterning (e.g., LELE is 2.5 times the cost of SE). SAQP: Self-aligned quadruple patterning. EUV: Extreme UV. LELELE: Litho etch litho etch litho etch.