Akram A. Salman

Field Effect Diode (FED): A novel device for ESD protection in deep sub-micron SOI technologies

In this paper the authors present the field effect diode (FED) as a novel device with a new approach for ESD protection in SOI. Device parameters are identified and optimized to achieve optimum ON and OFF behavior. Furthermore, the authors present two ways the FED can be used in an ESD protection scheme: in I/O clamping and in a high-voltage supply clamp

SOI Field-Effect Diode DRAM Cell: Design and Operation

A dynamic RAM cell based on the field-effect diode (FED) is presented, and its operation is described and explained with the help of numerical device simulations. This new cell resembles the thin capacitively coupled thyristor (TCCT) cell in concept and operation, however it has important advantages. These advantages derive from the fact that the thyristor-like mode of operation of the FED is gate induced, whereas the TCCT is an actual, built-in thyristor. High read 0/1 current margin, fast write/read time, good retention, and densely packed cells are obtained.

Design and Characterization of ESD Protection Devices for High-Speed I/O in Advanced SOI Technology

This paper focuses on the characterization, modeling, and design of electrostatic discharge (ESD) protection devices such as the gated diode, the bulk substrate diode, and the double-well field-effect diode (DWFED) in 45 nm silicon-on-insulator technology. ESD protection capabilities are investigated using very fast transmission line pulsing tests to predict a devices performance in charged device model (CDM) ESD events. Device capacitance, which is critical for high-speed input/output performance, is evaluated, and biasing schemes and processing techniques are proposed to reduce the parasitic capacitance during normal operating conditions. Technology computer-aided design simulations are used to interpret the physical effects. The implementation of devices for meeting CDM protection requirements is discussed. Evaluation results identify DWFED as a promising candidate for the pad-based local-clamping scheme.

Field effect diode for effective CDM ESD protection in 45 nm SOI technology

In this paper, the improved field-effect diode (FED) has been characterized and modeled in 45 nm silicon-on-insulator (SOI) technology. It has been experimentally shown to be suitable for pad-based local clamping under normal supply voltage (Vdd) range (below 1 V) in high-speed integrated circuits. ESD protection capabilities are investigated using very fast transmission line pulse (VF-TLP) tests to predict the devices performance in charged device model (CDM) ESD events. The FEDs advantages in improving transient turn-on behavior and reducing DC leakage current have been analyzed and compared with other Silicon-Controlled-Rectifier (SCR)-based SOI device variations. Technology CAD (TCAD) simulations are used to interpret the turn-on behavior and the physical effects. Process tradeoffs have been evaluated. The work prepares the device for being directly applied to high-speed Input/Output (I/O) circuit and it addresses the severe challenge in CDM ESD protection. The improved device enables the adoption of local clamping scheme that expands the ESD design window.

ESD protection for SOI technology using an under-the-box (substrate) diode structure

This paper presents a new integrated silicon-on-insulator (SOI) substrate-diode (SUBD) structure for an electrostatic-discharge (ESD) protection of the SOI I/O circuits. The diode is built under the buried oxide, within the substrate region of the SOI wafer, without additional steps to the conventional SOI CMOS process. This paper shows that the ESD protection level can reach four times the level of the standard SOI lateral-diode structure. This paper presents the device and process simulation results to demonstrate the effect of self-heating in both the standard SOI lateral and substrate diodes, and to demonstrate how to optimize the SUBD structure using a deep n-well implant

Engineering optimal high current characteristics of high voltage DENMOS

This paper demonstrates the dramatic improvement in ESD performance of HV DENMOS and LDMOS obtained by using selective drain extension silicide blocking (SBLK). The results are validated through 3D TCAD and TLP measurements on different technologies. Measured D.C. Id-Vd characteristics show minimal performance impact due to the addition of SBLK region.

ESD protection for SOI technology using under-the-BOX (substrate) diode structure

In this paper we will present a new integrated SOI substrate diode structure for ESD protection of SOI I/O circuits that is built under the buried oxide of the SOI wafer using a standard CMOS process. We will show that the protection level can reach four times what is achieved by the standard-lateral SOI diode structure. We will also show device and process simulation results to understand the self-heating effect of both standard-SOI and substrate diodes, as well as how to optimize the structure using a deep N-well implant.

Overshoot-induced failures in forward-biased diodes: A new challenge to high-speed ESD design

We report a new challenge to IEC protection of high-speed devices caused by current filamentation due to voltage-overshoot effects in forward-biased diodes. While well understood in reverse-biased junctions, filamentation has never been reported in forward-biased junctions, which are often used in high-speed designs such as USB3 and HDMI. An analytical model is presented to estimate the voltage overshoot as a function of rise-time and bias conditions to predict the trade-offs inherent in low-capacitance ESD diodes.

Double well field effect diode: Lateral SCR-like device for ESD protection of I/Os in deep sub micron SOI

The double well field effect diode (DWFED), an SOI SCR-like device for ESD protection of I/O circuits, is presented. The effect of device and process parameters on the diode on-voltage is examined, and the TLP and VFTLP characteristics of the DWFED are compared with those of the SOI lateral diode. It is shown how to use the DWFED for local clamping ESD protection, with a diode-like It2 level.

I/O Architecture For Improved ESD Protection In Deep Sub-Micron SOI Technologies

In this paper, the I/O structure described is based on a state of the art 65nm SOI technology designed for SRAM and logic applications (Leobandung et al, 2005). It is a twin-well partially depleted SOI (PDSOI) CMOS technology with gate oxide thicknesses of 1.05nm (SG) and 2.35nm (DG)