Gianluca Boselli

RF CMOS on high-resistivity substrates for system-on-chip applications

The use of a high-resistivity substrate extends the capability of standard digital CMOS technology to enable the integration of high-performance RF passive components. The impact of substrate resistivity on the key components of RF CMOS for system-on-chip (SoC) applications is discussed. The comparison includes the transistor, transmission line, inductor, capacitor and varactor, as well as the noise isolation. We also discuss the integration issues including latch-up and well-well isolation in a 0.35-/spl mu/m Cu metal pitch, 0.1-/spl mu/m-gate-length RF CMOS technology.

Latch-up in 65nm CMOS technology: a scaling perspective

In this study, through a detailed analysis of the last four CMOS technology nodes, targeting similar applications, the intrinsic latch-up process sensitivity is investigated in an attempt to assess in which measure latch-up will continue to be a major reliability concern for future CMOS technologies.

0.1 /spl mu/m RFCMOS on high resistivity substrates for system on chip (SOC) applications

This paper describes the impact of substrate resistivity on the key components of the radio frequency (RF) CMOS for the system on chip (SOC) applications. The comparison includes the transistor, inductor, capacitor, noise isolation, latch-up as well as the well-to-well isolation in a 0.1 /spl mu/m (physical gate length) CMOS technology.

Drain Extended NMOS High Current Behavior and ESD Protection Strategy for HV Applications in Sub-100nm CMOS Technologies

In this work the high current behavior of drain-extended nMOS transistors (DEnMOS) built in a state-of-the-art 65nm CMOS technology were investigated. It shown that a sufficient level of ESD robustness (I T2~2mA/mum) can be achieved through substrate biasing. The concept will be exploited to build robust ESD protections

ESD and latch-up reliability for nanometer CMOS technologies

Considerable research during the 80s and 90s laid the foundation for a deeper understanding of the ESD high current device physics and the subsequent protection design techniques required to achieve ESD reliability for numerous applications (Amerasekera and Duvvury, 2001; Dabral and Maloney,1998). Indeed, at every node a different parameter has had the most influencing effect, especially on ESD. This paper will review the recent trends as the industry moves towards nanometer technologies. New circuit applications are also discussed to introduce the upcoming critical issues for ESD and LU design.

Investigations on double-diffused MOS (DMOS) transistors under ESD zap conditions

In this paper we analyzed, through experiments and 2D simulations, the behaviour under high reverse voltages of a DMOS transistor. It turned out that the drift diffusion region (resistor) between the drain contact and p-diffusion region (PI) plays an important role both in the switching-on of the parasitic bipolar structure and in the failure mechanism.

Engineering optimal high current characteristics of high voltage DENMOS

This paper demonstrates the dramatic improvement in ESD performance of HV DENMOS and LDMOS obtained by using selective drain extension silicide blocking (SBLK). The results are validated through 3D TCAD and TLP measurements on different technologies. Measured D.C. Id-Vd characteristics show minimal performance impact due to the addition of SBLK region.

Overshoot-induced failures in forward-biased diodes: A new challenge to high-speed ESD design

We report a new challenge to IEC protection of high-speed devices caused by current filamentation due to voltage-overshoot effects in forward-biased diodes. While well understood in reverse-biased junctions, filamentation has never been reported in forward-biased junctions, which are often used in high-speed designs such as USB3 and HDMI. An analytical model is presented to estimate the voltage overshoot as a function of rise-time and bias conditions to predict the trade-offs inherent in low-capacitance ESD diodes.

Technology scaling effects on the ESD design parameters in sub-100 nm CMOS transistors

A new phenomenon, reported in this paper for the first time, produces a dramatic reduction of the nMOS and pMOS triggering voltage (V/sub Tl/) under ESD conditions for an ultra-scaled 90 nm CMOS technology used in high performance applications. This V/sub Tl/ reduction is caused by the merging of pocket implants in short gate length transistors. This has a serious impact on the ESD sensitivity of output drivers, placing restrictions on the design of effective protection devices and burn-in voltage during product screening.

Prediction of Charged Device Model Peak Discharge Current for Microelectronic Components

This paper presents a computationally efficient methodology to predict the peak current stress experienced by a microelectronic component during a field-induced charge device model (FICDM) electrostatic discharge test. The methodology is applied to a variety of IC components in different types of packages; the peak current values obtained from simulations agree well with those obtained from FICDM measurements.