Ann Concannon

Investigation of reverse recovery effects on the SOA of integrated high frequency power transistors

Switching frequency and switching losses are the dominating factors in power conversion applications. These factors can be controlled at technology development or at IC design with different trade-offs. In this paper we introduce a technique to measure safe operating area (SOA) under high frequency switching conditions - primarily, when the power LDMOS body diode is undergoing reverse-recovery. We show that this new SOA is more conservative than the electrical SOA and defines a diminished boundary for high frequency and high reverse injection operations. With this technique we look at the impact on specific design parameters in commonly used LDMOS topologies in an advanced BCD technology. Furthermore with the help of numerical simulations and careful metrological observations we discuss the phenomena leading to device performance limits useful for IC and device designers. Failure analysis of devices at product level and controlled failures created in standalone devices at wafer-level are examined.

Improved inductive-system-level IEC ESD performance for automotive applications using mutual ballasted ESD protection technique

Abstract A new ESD failure mode under inductive IEC stress of automotive Controller Area Network (CAN) bus is identified. Inductor saturation causes increase of the rise-time from 1xa0ns to ~xa020xa0ns, leading to non-uniform conduction in the bidirectional ESD protection circuit. A novel mutual ballasting layout technique is introduced to recover the system level ESD performance.

Impact of sub-threshold SOA on ESD protection schemes

SOA (safe operating area) at subthreshold gate voltages are typically not of interest during normal operation. Under ESD conditions, however, the device could be biased in the subthreshold regime. In this paper we discuss the impact of subthreshold gate voltages on the SOA boundary of LDMOS devices and its implications to ESD design.

HBM failures induced by ESD cell turn-off and circuit interaction with ESD protection

Limited ESD simulations are often combined with topology checks to avoid ESD weaknesses arising from transient circuit interaction with ESD protection. In this work, we focus on a product designed using such a methodology exhibiting HBM failures. The failures were narrowed down to circuit interaction at ESD cell turn-on and turn-off.