Farzan Farbiz

Modeling and Understanding of External Latchup in CMOS Technologies—Part I: Modeling Latchup Trigger Current

This paper elucidates the roles of substrate majority and minority carriers in triggering external latchup, where the term external signifies that the substrate current injection occurs at a location away from the p-n-p-n structure. Circuit-level models are presented that allow one to identify the worst case testing condition and to simulate the value of the latchup trigger current. The model captures the effect of guard rings. The simulation results are compared to measurement results, and good agreement is observed, for a variety of CMOS technologies.

Analytical modeling of external latchup

A model is presented for external latchup. The effects of spacing, temperature, supply voltage and layout are captured in the model. The model shows a good fit to data in two different technologies, RF-CMOS and SmartMOS.

Understanding transient latchup hazards and the impact of guard rings

An experimental study of transient latchup is conducted. Measurements are performed on test structures fabricated in 90-nm and 130-nm CMOS technologies. The worst case testing conditions differ for static and transient latchup. Device simulation is used to understand the measurement results. P-well and N-well guard rings are evaluated under transient test conditions.

Engineering optimal high current characteristics of high voltage DENMOS

This paper demonstrates the dramatic improvement in ESD performance of HV DENMOS and LDMOS obtained by using selective drain extension silicide blocking (SBLK). The results are validated through 3D TCAD and TLP measurements on different technologies. Measured D.C. Id-Vd characteristics show minimal performance impact due to the addition of SBLK region.

Overshoot-induced failures in forward-biased diodes: A new challenge to high-speed ESD design

We report a new challenge to IEC protection of high-speed devices caused by current filamentation due to voltage-overshoot effects in forward-biased diodes. While well understood in reverse-biased junctions, filamentation has never been reported in forward-biased junctions, which are often used in high-speed designs such as USB3 and HDMI. An analytical model is presented to estimate the voltage overshoot as a function of rise-time and bias conditions to predict the trade-offs inherent in low-capacitance ESD diodes.

Modeling and Understanding of External Latchup in CMOS Technologies—Part II: Minority Carrier Collection Efficiency

The n-wells of the parasitic p-n-p-n devices found in a CMOS layout will collect excess minority carriers from the chip substrate, potentially triggering latchup. This paper presents a model for the minority carrier collection efficiency of a given substrate current injector and collector pair; the model captures the effects of spacing, supply voltage, temperature, and current level. The model further describes the quantitative reduction in collection efficiency obtained by using guard rings. A good fit of the model to measurement results is observed in four different CMOS technologies.

Modeling of majority and minority carrier triggered external latchup

Circuit models are presented that allow one to identify the worst-case testing condition for external latchup and to simulate the value of the latchup trigger current. The models are valid under both moderate and high-level injection. A good fit between the model and the measurements is observed. The roles of substrate majority and minority carriers are elucidated.

Novel area-efficient techniques for improving ESD performance of Drain extended transistors

DEMOS devices have poor ESD robustness due to kirk effect induced snapback. Isolated DEMOS devices, in addition to the kirk effect induced second snapback, are also vulnerable to failures induced by the parasitic NPN to isolation. In addition, we demonstrate here, that some DEMOS devices show intrinsically non-scalable breakdown current (IT1) behavior due to insufficient body resistance. We then demonstrate techniques to restore IT1 scalability in these devices. We finally demonstrate the effectiveness of using selectively SBLKed drain fingers to enable self protection in small DEMOS devices.

An Investigation of External Latchup

Circuits are more susceptible to external latchup at elevated temperatures not only because the PNPN trigger current is lowered, but also because the minority carrier collection efficiency is increased. Collection efficiency does not scale linearly with the dimensions of the N-well. PNPN structures that are oriented perpendicular to a substrate current injector are more susceptible to latchup than are those oriented parallel

EDA approaches in identifying latchup risks

In this paper we review latchup protection verification methods and EDA challenges. We demonstrate complex static and transient latchup scenarios requiring advanced connectivity analysis. Using various EDA verification flows and tools we study latchup problems associated with grounded n-wells, biased n-wells and parasitic thyristors formed during ESD events.