Aravind C. Appaswamy

Engineering optimal high current characteristics of high voltage DENMOS

This paper demonstrates the dramatic improvement in ESD performance of HV DENMOS and LDMOS obtained by using selective drain extension silicide blocking (SBLK). The results are validated through 3D TCAD and TLP measurements on different technologies. Measured D.C. Id-Vd characteristics show minimal performance impact due to the addition of SBLK region.

Overshoot-induced failures in forward-biased diodes: A new challenge to high-speed ESD design

We report a new challenge to IEC protection of high-speed devices caused by current filamentation due to voltage-overshoot effects in forward-biased diodes. While well understood in reverse-biased junctions, filamentation has never been reported in forward-biased junctions, which are often used in high-speed designs such as USB3 and HDMI. An analytical model is presented to estimate the voltage overshoot as a function of rise-time and bias conditions to predict the trade-offs inherent in low-capacitance ESD diodes.

Novel area-efficient techniques for improving ESD performance of Drain extended transistors

DEMOS devices have poor ESD robustness due to kirk effect induced snapback. Isolated DEMOS devices, in addition to the kirk effect induced second snapback, are also vulnerable to failures induced by the parasitic NPN to isolation. In addition, we demonstrate here, that some DEMOS devices show intrinsically non-scalable breakdown current (IT1) behavior due to insufficient body resistance. We then demonstrate techniques to restore IT1 scalability in these devices. We finally demonstrate the effectiveness of using selectively SBLKed drain fingers to enable self protection in small DEMOS devices.

Improving the long pulse width failure current of NPN in BiCMOS technology

The pulse width dependency of the failure current for NPN structures in a 0.18-μm BiCMOS technology is studied using measurements and TCAD simulation. The desired “Wunsch-Bell” behavior is not observed due to formation of current filaments in this device; however, the failure current for long pulse widths can be increased by layout changes.

State-of-the-art ESD protection devices and techniques for digital and analog technologies

This paper is a review of the latest advances in ESD protection for analog and digital technologies. The paper will introduce the latest ESD protection devices for FinFET and FDSOI technologies such as Field effect diode, Field effect resistor. We will introduce an example of innovation for analog ESD protection focusing on system level automotive applications namely Mutual ballasting layout technique.

Impact of sub-threshold SOA on ESD protection schemes

SOA (safe operating area) at subthreshold gate voltages are typically not of interest during normal operation. Under ESD conditions, however, the device could be biased in the subthreshold regime. In this paper we discuss the impact of subthreshold gate voltages on the SOA boundary of LDMOS devices and its implications to ESD design.