Akshay Visweswaran

All-Digital RF

We present a new all-digital RF in-phase/quadrature (I/Q) modulator, in which the orthogonal summing of the I and Q phase data signals is performed in separated interleaved time slots. By employing a 25% duty cycle for the I and Q signals, the modulator can directly reconstruct the continuous-time RF output signal using four digital switch arrays with a power combiner. To verify the proposed concept and its related design procedure, a 65-nm CMOS prototype is implemented. This prototype achieves 12.6-dBm peak output power with 20% peak drain efficiency at 2 GHz. The corresponding error vector magnitude (EVM) for a quadrature phase-shift keying constellation is 3.95% without any predistortion, while providing 6-dBm output power in a 64 quadrature amplitude modulation constellation with a related EVM and drain efficiency of 2.36% and 10%, respectively. The proposed circuit can be used as a pre-driver or a final transmit stage. The first-ever truly all-digital I/Q RF digital-to-analog converter prototype is thus experimentally demonstrated.

I/Q

Base-station (BTS) RX oscillator phase noise requirements between 600kHz and 3MHz are difficult to satisfy using a fully monolithic VCO fabricated in bulk-CMOS technology. The GSM-900-BTS and the DCS-1800-BTS RX specifications at 800kHz of -147dBc/Hz and -138dBc/Hz, respectively, are considered the most difficult to meet. In GSM mobile stations (MS), the transmit and receive bands are 20MHz apart, which sets a stringent TX phase noise requirement of -162dBc/Hz at 20MHz offset [1]. A VCO satisfying this inadvertently meets the relatively relaxed RX specification.

Modulator

We propose a novel digital I/Q modulator implemented in 65 nm CMOS technology. Using in-phase (I) and quadrature-phase (Q) clock signals with a 25% duty cycle, the modulator can directly construct the RF output signal using four transistor switch banks with a power combiner. The circuit achieves 12.6 dBm peak output power and 20% peak drain efficiency at 2 GHz. While providing 6 dBm output power, the error vector magnitude (EVM) is 3.7% and could be used as pre-driver or final transmit stage. The first ever all-digital I/Q RF-DAC prototype is thus experimentally demonstrated.

A clip-and-restore technique for phase desensitization in a 1.2V 65nm CMOS oscillator for cellular mobile and base stations

Reduced phase noise conversion in a monolithic oscillator suitable for basestation applications is realized by hard limiting and subsequently restoring the resonating waveform. Overdriven transistors hard limit the drain voltage swing and it is shown analytically that this desensitizes the oscillation phase to circuit noise. A pair of tuned, 1:2 step-up transformers in the feedback path restore the fundamental frequency component with sufficient gain to overdrive the transistors forming the oscillator core, with greater selectivity than an equivalent LC tank. The 8 GHz, 65 nm CMOS oscillator prototype targeting the GSM-900 base-station specification consumes 32 mA from 1.5 V. Normalized to 915 MHz, the phase noise measured at 1 MHz offset is -147.7 dBc/Hz, validating predictions from theory and simulation. The measured frequency pushing is less than 16 MHz/V.

A 2-GHz digital I/Q modulator in 65-nm CMOS

In this paper we investigate benefits of a recently introduced clip-and-restore (C&R) oscillator for ultra-low phase noise RF applications and reconsider the original choices in light of further insight into the oscillator behavior. We also tackle undesired resonance frequencies and exploit them to facilitate clipping with proper choices of tuning capacitances. Based on the new theory, the proposed oscillator was implemented in 65-nm CMOS and verified to achieve 4 dB better phase noise and 1.8 dB better FoM than the original C&R oscillator, thus making it the lowest phase noise CMOS oscillator ever published. The measured phase noise is -145 dBc/Hz at a 3 MHz offset from a 4.2 GHz carrier. The resulting average FoM is 191 dBc/Hz and varies less than 2 dB across the tuning range. It covers the 7.28.7 GHz frequency band for a 19% tuning range, drawing 32 mA from a 1.3 V power supply.

A Low Phase Noise Oscillator Principled on Transformer-Coupled Hard Limiting

An FM demodulator operating across 8GHz IF bandwidth for application in low-power, wideband heterodyne receivers is presented. A 4-stage ring oscillator is frequency modulated by a wideband input. Locking to 1/4th the input frequency, it divides the FM deviation by four, thereby reducing the energy required for wideband demodulation to 0.75nJ/bit. Autocorrelation of the quadrature-phased outputs using a new low-power folded CMOS mixer is capable of detecting FM up to 400Mb/s over 2-10GHz IF. The inductorless 65nm CMOS prototype circuit occupies 0.17mm2 and dissipates 3mW from 1.2V.

Ultra-low phase noise 7.2–8.7 Ghz clip-and-restore oscillator with 191 dBc/Hz FoM

Fine frequency tuning based on injection locking applicable to analog and digitally-controlled LC quadrature-oscillators is proposed. The operating frequency varies linearly with relative strength of the controllable injected signal with a slope proportional to 1/2Q. Its linear characteristic makes it suitable for digitization. An 8 GHz prototype fabricated in 65nm CMOS, operating from a 1.2 V supply, exhibits linear fine-tuning of 60 MHz at an output swing where digital switches and CMOS varactors would encounter fine-tuning limitations. For 10 mA drawn by differential oscillator cores, the phase noise at 1 MHz, varies by only 1.15 dB, and quadrature error from 0.3-1.6 degrees over the fine-tuning range. The deviation of the fine-tuning from a linear response is less than 4%.

An FM demodulator operating across 2–10GHz IF

A low-power FM demodulator operating across a 2–10-GHz IF bandwidth for its application in wideband heterodyne receivers is presented. A four-stage ring oscillator locks to one-fourth of the input FM, thereby reducing the energy required for wideband demodulation. The measurements show that the oscillator is capable of locking to at least a modulating frequency of 400 MHz, and further testing is limited by the FM source. Linear demodulation of the quadrature-phased outputs is realized using a low-power folded CMOS mixer, even as the fractional bandwidth of the input FM approaches unity. The inductorless 65-nm CMOS prototype occupies 0.17 mm2 and dissipates 3.2 mW from 1.2 V at the quiescent point. The measured SNR sensitivity is 8 dB and the demodulator bit-error rate is 0.1% at 10 Mb/s for a 45-mVpp input signal at IF.

Fine frequency tuning using injection-control in a 1.2V 65nm CMOS quadrature oscillator

In this contribution we present a custom test-bench capable of delivering multi-path mm-wave signals with amplitude and phase control to an on-wafer environment. The setup employs direct IQ up-conversion in the 7.5GHz to 10GHz band, with high resolution DACs to modulate both amplitude and phases of n coherent LO signals. Signal amplification followed by frequency multiplication generates mm-wave signals in the 30 to 40GHz range. An amplitude pre-distortion technique, to level the IQ mixer output power versus phase angle, and a calibration technique are developed to achieve accurate amplitude and phase control between the signals at the wafer probe-tip level.

Injection-Locked Wideband FM Demodulation at IF

A wideband, fully differential, 3-stage class-AB amplifier capable of operation at rates beyond 100 Mbps is described. Common-mode feedback is applied to increase output drive capability and reduce bias-dependent crossover distortion when operating in class-AB from a low supply voltage. Drawing 3.9mA from a nominal VDD of 1.2V in 65nm CMOS, the 0.052mm2 amplifier delivers 1.6V swing across a 50Ω load with THD+N of 82.6dB at 150kHz in the unity-gain configuration.