Alain Greiner

SPIN: A Scalable, Packet Switched, On-Chip Micro-Network

This paper presents the SPIN micro-network that is a generic, scalable interconnect architecture for system on chip. The SPIN architecture relies on packet switching and point-to-point bi-directional links between the routers implementing the micro-network. SPIN gives the system designer the simple view of a single shared address space and provides a variable number of VCI compliant communication interfaces for both initiators (masters) and targets (slaves). Performance comparisons between a classical PI-bus based interconnect and the SPIN micro-network are analyzed.

An Efficient TLM/T Modeling and Simulation Environment Based on Conservative Parallel Discrete Event Principles

The paper presents an innovative simulation scheme to speed-up simulations of multi-clusters multi-processors SoCs at the TLM/T (transaction level model with time) abstraction level. The hardware components of the SoC architecture are written in standard SystemC. The goal is to describe the dynamic behavior of a given software application running on a given hardware architecture (including the dynamic contention in the interconnect and the cache effects), in order to provide the system designer with the same reliable timing information as a cycle accurate simulation, with a simulation speed similar to a TLM simulation. The key idea is to apply parallel discrete event simulation (PDES) techniques to a collection of communicating SystemC SC-THREAD. Experimental results show a simulation speedup of a factor up to 50 versus a BCA simulation (bus cycle accurate), for a timing error lower than 10-3

Estimating energy consumption for an MPSoC architectural exploration

Early energy estimation is increasingly important in MultiProcessor System-On-Chip (MPSoC) design. Applying traditional approaches, which consist in delaying the estimation until the architectural layout has been produced, is inefficient and prevents the rapid exploration of alternative architectures. In this paper, we present a framework for architectural exploration as part of MPSoC design. Our framework allows configurations that offer a good performance/energy tradeoffs to be found early in the design flow. The hardware components, described at the Cycle-Accurate Bit-Accurate (CABA) level of SystemC, were taken from the SoCLib library. For each component in the library, we developed an energy model using both physical measurements and analytical models of energy consumption. These models indicate a good accuracy/speed tradeoffs. Plugging the energy models into the SoCLib architectural simulator makes it easy to estimate the applications performance and energy consumption. The effectiveness of our method is illustrated through design space exploration (DSE) for a parallel signal processing application.

A Generic Instruction Set Simulator API for Timed and Untimed Simulation and Debug of MP2-SoCs

This paper presents a method for designing SystemC-compliantInstruction Set Simulators (ISS) that address three of the majorproblems system designers are faced with when modeling MP-SoCsarchitectures: the multiple levels of abstraction of the simulationmodels supporting the design space exploration, the simulation speed,and the debug of the multithreaded embedded application. First, thispaper presents the ISS API and principles; then it describes howthe same ISS can support SystemC simulation at several abstractionlevels: untimed transaction level, approximately timed transactionlevel, and cycle accurate; then, it describes how the proposed ISS APIhas been used by six different laboratories - in the framework of theSoCLib project - to share the same L1 cache simulation model, and towrap seven different processor cores in the same generic wrappers.Finally we demonstrate how the proposed API has been exploited todevelop a generic debug and instrumentationinfrastructure that can be used for all the processor cores, and allthe abstraction levels supported by the SoCLib virtual prototypingplatform.

At-Speed Testing of Core-Based System-on-Chip Using an Embedded Micro-Tester

In SoC designs, limited test access to internal cores, low-cost external testers lack of accuracy and slow frequencies make application of at-speed tests impractical. Therefore, this paper presents an embedded micro-tester for testing IEEE1500-compliant SoCs. In the proposed approach, the test program is no more executed by the external tester but by the embedded micro-tester. Under the control of the embedded SoC microprocessor, the micro-tester executes the test programs stored outside of the SoC in an external memory. The micro-tester supports stuck-at testing as well as both at-speed testing techniques: launch-on-last-shift (LOLS) and launch-on-capture (LOC). Using the ITC02 benchmarks, experimental results are presented: test application time, test data volume and area overhead

STEPS: experimenting a new software-based strategy for testing SoCs containing P1500-compliant IP cores

This paper presents STEPS, an innovative software-based approach for testing P1500-compliant SoCs. STEPS is based on the concept that the ATE is not considered as an initiator applying vectors to the SoC test pins but rather as a target, a huge repository of 32-bits test data and control commands. The ATE is connected to the functional SoC external RAM controller interface. The only additional test component in the SoC is a P1500 test processor that converts test data into serial P1500 streams. This paper applies the STEPS methodology to SoCs containing a VCI-compliant interconnect, a microprocessor, P1500-compliant IP cores and an external RAM controller interface. Using the ITC02 SoC benchmarks, a comparison is done between the STEPS architecture and a classical bus-based strategy.

Analog design for reuse-case study: very low-voltage /spl Delta//spl Sigma/ modulator

This paper presents the complete design methodology of a very low-voltage AX third-order modulator from highlevel specifcations down to layout. Behavioral models taking into account cell non-idealities are developed and used to map pe~ormance specijications to lower levels. Emphasis has been made on eventual design reuse through design plans and layout templates in a layout-oriented circuit design approach. The modulator has been designed for two different technologies demonstrating the suitability of the methodology for very high performance mixed-signal circuits. Moreover; the same design knowledge has been successfully reused in another fourth-order modulator.This paper presents the complete design methodology of a very low-voltage /spl Delta//spl Sigma/ third-order modulator from high-level specifications down to layout. Behavioral models taking into account cell nonidealities are developed and used to map performance specifications to lower levels. Emphasis has been made on eventual design reuse through design plans and layout templates in a layout-oriented circuit design approach. The modulator has been designed for two different technologies demonstrating the suitability of the methodology for very high performance mixed-signal circuits. Moreover the same design knowledge has been successfully reused in another fourth-order modulator.

Fully distributed initialization procedure for a 2D-Mesh NoC, including off-line BIST and partial deactivation of faulty components

In this paper, we present an embedded, at speed, off-line, and fully distributed initialization procedure for 2D-Mesh Network-on-Chip (NoC). This procedure is executed at power boot, and targets the detection and the deactivation of the faulty routers and/or faulty communication channels. The final objective is fault tolerance. The proposed procedure is able to clean the NoC from all destructive malfunctions induced by permanent hardware failures. This initialization procedure has been implemented in a reconfigurable version of the DSPIN micro-network, and evaluated from the point of view of Stuck-at fault coverage, and area overhead.

T-Proc: An Embedded IEEE1500-Wrapped Cores Tester

This paper presents a software-based approach for testing IEEE1500-compliant SoCs. In the proposed approach, the test program is no more executed by the external-traditional tester but by the SoC itself. The novel feature is the use of a dedicated test processor called T-Proc embedded onto the SoC to test the components. Under the control of the embedded SoC microprocessor, the test processor executes the test programs stored in the outside external memory, through a functional embedded external RAM controller interface. Using the ITC02 SoC benchmarks a comparison is done between T-Proc and a classical bus-based test strategy

Localization of damaged resources in NoC based shared-memory MP2SOC, using a Distributed Cooperative Configuration Infrastructure

In this paper, we present a software approach for localization of faulty components in a 2D-mesh Network-on-Chip, targeting fault tolerance in a shared memory MP2SoC architecture. We use a pre-existing and distributed hardware infrastructure supporting self-test and de-activation of the faulty components (routers and communication channels), that are transformed into “black hole”. We detail the software method used to localize these “black holes”, and centralize the information in a single point, where a modified global routing function can be defined. This embedded software makes an extensive use of a distributed fault-tolerant configuration firmware assisted by a Distributed Cooperative Configuration Infrastructure (DCCI), that is also presented. Finally, “black hole” detection and localization coverage is evaluated.