Cesar Albenes Zeferino

SoCIN: a parametric and scalable network-on-chip

Networks-on-chip (NoCs) interconnection architectures, to be used in future billion-transistor systems-on-chip (SoCs), meet the major communication requirements of these systems, offering, at the same time, reusability, scalability and parallelism in communication. Furthermore, they cope with other issues like power constraints and clock distribution. Currently, there are a number of research works which explore different features of NoCs. In this paper, we present SoCIN, a scalable network based on a parametric router architecture to be used in the synthesis of customized low cost NoCs. The architecture of SoCIN and its router are described, and some synthesis results are presented.

SPIN: A Scalable, Packet Switched, On-Chip Micro-Network

This paper presents the SPIN micro-network that is a generic, scalable interconnect architecture for system on chip. The SPIN architecture relies on packet switching and point-to-point bi-directional links between the routers implementing the micro-network. SPIN gives the system designer the simple view of a single shared address space and provides a variable number of VCI compliant communication interfaces for both initiators (masters) and targets (slaves). Performance comparisons between a classical PI-bus based interconnect and the SPIN micro-network are analyzed.

RASoC: a router soft-core for networks-on-chip

The building block of a network-on-chip (NoCs) is its router. It is responsible to switch the channels which forward the messages exchanged by the cores attached to the NoC, and the costs and performance of the NoC strongly depends on the router architecture. In this paper, we present RASoC, a router architecture intended to be used in the building of low area overhead NoCs for embedded systems. The difference among RASoC and current routers relies on its implementation as a parameterized VHDL model, which improve the reuse of RASoC in the synthesis of NoCs with different sizes, and allows the tuning of the NoC parameters in order to meet the requirements of the target application. The paper presents details of RASoC architecture, the structure of the VHDL model and some experimental results which show the scalability of the soft-core and its costs.

The impact of NoC reuse on the testing of core-based systems

The authors propose the reuse of on-chip networks for the test of core-based systems that use this platform. Two possibilities of reuse are proposed and discussed with respect to test time minimization. An algorithm exploiting network characteristics to reduce test time is presented. Experimental results show that the parallelization capability of the network can be exploited to reduce the system test time, whereas area and pin overhead are strongly minimized.

A study on communication issues for systems-on-chip

Present days cores composing a system-on-chip might be interconnected by means of both dedicated channels or shared buses. Nevertheless, future systems will have strong requirements on reusability and communication performance, which will constrain the use of such interconnect systems. An emerging approach, the networks-on-chip (NOCs), will potentially fulfill those requirements, because NOCs are reusable and their communication performance gracefully scales with the system growth. However, it is still not clear when the use of NOCs will become mandatory. This work introduces some studies to define the switching point when NOCs become the preferred communication architecture. A bus and a NOC are modeled and compared by using a set of mathematical models.

ParIS: a parameterizable interconnect switch for networks-on-chip

Networks-on-Chip (NoCs) emerge as the solution for the problem of interconnecting cores (or IPs) in systems-on-chip (SoCs) which require reusable and scalable communication architectures. The building block of a NoC is its router (or switch), whose architecture has great impact on the costs and on the performance of the network. This work presents a parameterizable router architecture for NoCs which is based on a canonical template and on a library of building components offering different alternatives and implementations for the circuits used for packet forwarding in a NoC. Such features allow to explore the NoC design space in order to obtain a router configuration which best fits the performance requirements of a target application at lower silicon costs. We describe the router architecture and present some synthesis results which demonstrate the feasibility of this new router.

Communication Architectures for System-on-Chip

The analysis of the communication architecture and its associated synthesis process has grown in importance in the era of System-On-Chip (SoC) devices, since one is moving towards more complex systems, made by several processing elements (cores), with heterogeneous behavior. In many cases, the choice for a communication architecture can be the most crucial factor to meet design constraints. This goal of this work is to define and implement algorithms devoted to analyzing and selecting those communication architectures that better match the user defined system constraints, in an integrated design environment.

Adding mechanisms for QoS to a network-on-chip

Networks-on-Chip (NoCs) are recognized as an interconnection architecture with capability of providing scalable performance, which is an important feature for communication in future SoCs (Systems-on-Chip) with high density. Most NoC models proposed in the last years are best effort networks, which offer no guarantees of Quality of Service (QoS) in communication. However, many of the applications envisaged for future SoCs have QoS requirements. In this work, they are presented the deployment of three different mechanisms for providing QoS to a best effort NoC: circuit switching, virtual channels and virtual channels combined with aging scheduling. All the deployments were made in VHDL, and testbenches were used to verify their correct operation. SystemC-based models were also described in order to evaluate the impact of these techniques on the network performance. Results show how the implemented techniques improve the ability of the network in meeting QoS requirements.

Mechanisms to Provide Fault Tolerance to a Network-on-Chip

The constant reduction in the components size of integrated circuits, as well as higher operating frequencies, increases the vulnerability to internal and external noise sources. These noises can cause a failure in any component, affecting the functioning of the system as a whole. Systems-on-Chip (SoCs) with dozens of cores are based on Networks-on-Chip (NoCs), and require networks that are able to detect and prevent a fault in leading to a system failure and an application malfunction. In this context, this work aims at evaluating solutions to increase the reliability and availability of a NoC, implementing mechanisms for error detection and correction. Spatial and information redundancy techniques were applied in order to protect the network against Single Event Upset (SEU) faults. The applied techniques ensured the correct operation of the network in the presence of faults, with low impact to the performance and with acceptable silicon costs.

XIRU: Interface de Rede Extensível para Integração de Núcleos a uma Rede-em-Chip

Para a integracao dos nucleos de um sistema integrado a uma NoC ( Network-on-Chip ), e necessario o uso de interfaces de comunicacao que realizem a adaptacao do protocolo dos nucleos ao da rede e que oferecam os servicos de comunicacao necessarios aos nucleos. Este artigo descreve a arquitetura de uma interface de rede extensivel para a integracao de nucleos a NoC SoCIN ( System-on-Chip Interconnection Network ). A interface proposta utiliza uma arquitetura estruturada em tres camadas que realizam a adaptacao do protocolo, o empacotamento/desempacotamento de dados e o envio/recepcao de pacotes, entre outros servicos. O artigo descreve a arquitetura da interface de rede e apresenta os resultados de sua validacao e sintese em silicio.