Alan D. Tipton

Impact of Low-Energy Proton Induced Upsets on Test Methods and Rate Predictions

Direct ionization from low energy protons is shown to cause upsets in a 65-nm bulk CMOS SRAM, consistent with results reported for other deep submicron technologies. The experimental data are used to calibrate a Monte Carlo rate prediction model, which is used to evaluate the importance of this upset mechanism in typical space environments. For the ISS orbit and a geosynchronous (worst day) orbit, direct ionization from protons is a major contributor to the total error rate, but for a geosynchronous (solar min) orbit, the proton flux is too low to cause a significant number of events. The implications of these results for hardness assurance are discussed.

Multiple-Bit Upset in 130 nm CMOS Technology

The probability of proton-induced multiple-bit upset (MBU) has increased in highly-scaled technologies because device dimensions are small relative to particle event track size. Both proton-induced single event upset (SEU) and MBU responses have been shown to vary with angle and energy for certain technologies. This work analyzes SEU and MBU in a 130 nm CMOS SRAM in which the single-event response shows a strong dependence on the angle of proton incidence. Current proton testing methods do not account for device orientation relative to the proton beam and, subsequently, error rate prediction assumes no angular dependencies. Proton-induced MBU is expected to increase as integrated circuits continue to scale into the deep sub-micron regime. Consequently, the application of current testing methods will lead to an incorrect prediction of error rates

Characterizing SRAM Single Event Upset in Terms of Single and Multiple Node Charge Collection

A well-collapse source-injection mode for SRAM SEU is demonstrated through TCAD modeling. The recovery of the SRAMs state is shown to be based upon the resistive path from the p+ -sources in the SRAM to the well. Multiple cell upset patterns for direct charge collection and the well-collapse source-injection mechanisms are predicted and compared to SRAM test data.

Device-Orientation Effects on Multiple-Bit Upset in 65 nm SRAMs

The effects of device orientation on heavy ion-induced multiple-bit upset (MBU) in 65 nm SRAMs are examined. The MBU response is shown to depend on the orientation of the device during irradiation. The response depends on the direction of the incident ion to the n- and p-wells of the SRAM. The MBU response is simulated using Monte Carlo methods for a space environment. The probability is calculated for event size. Single-bit upsets in the space environment account for 90% of all events with exponentially decreasing probabilities of larger MBU events.

Laser-Induced Current Transients in Silicon-Germanium HBTs

Device-level current transients are induced by injecting carriers using two-photon absorption from a subbandgap pulsed laser and recorded using wideband transmission and measurement equipment. These transients exhibit three distinct temporal trends that depend on laser pulse energy as well as the transverse and vertical charge generation location. The nature of the current transient is controlled by both the behavior of the subcollector-substrate junction and isolation biasing. However, substrate potential modulation, due to deformation of the subcollector-substrate depletion region, is the dominant mechanism affecting transient characteristics.

Increased Rate of Multiple-Bit Upset From Neutrons at Large Angles of Incidence

Neutron interactions with terrestrial systems produce soft errors, increasing the failure-in-time (FIT) rate of advanced CMOS circuits. These neutron-induced errors are a critical reliability problem facing advanced technologies. This paper reports the accelerated neutron testing on a 90-nm CMOS SRAM that exhibits an increased multiple-bit upset FIT rate from neutrons at large angles of incidence. The modeling of these data is used to predict the reliability of ground-based systems.

Evidence for Lateral Angle Effect on Single-Event Latchup in 65 nm SRAMs

Single event latchup (SEL) in a 65 nm CMOS SRAM technology due to heavy ions is observed and device sensitivity is shown to be a strong function of lateral beam orientation, angle of incidence, and temperature. Experimental results show the importance of testing at multiple lateral beam orientations to properly characterize device sensitivity.

High Energy Neutron Multiple-Bit Upset

Neutron-induced multiple-bit upsets (MBU) in a 90 nm CMOS SRAM are examined using Monte-Carlo simulations. While the single-bit upset (SBU) cross section is nearly independent of angle, the probability of MBU increases for neutrons incident at grazing angles.

Radiation Test Results of Candidate Spacecraft Parts for the Applied Physics Laboratory

The radiation responses of candidate spacecraft digital-to-analog converters (DACs) and digital synthesizers are presented. Candidate electronics are evaluated for total ionizing dose and single event effects.