Jonathan A. Pellish

Single-Event Upsets and Multiple-Bit Upsets on a 45 nm SOI SRAM

Experimental results are presented on single-bit-upsets (SBU) and multiple-bit-upsets (MBU) on a 45 nm SOI SRAM. The accelerated testing results show the SBU-per-bit cross section is relatively constant with technology scaling but the MBU cross section is increasing. The MBU data show the importance of acquiring and analyzing the data with respect to the location of the multiple-bit upsets since the relative location of the cells is important in determining which MBU upsets can be corrected with error correcting code (ECC) circuits. For the SOI SRAMs, a large MBU orientation effect is observed with most of the MBU events occurring along the same SRAM bit-line; allowing ECC circuits to correct most of these MBU events.

Impact of Low-Energy Proton Induced Upsets on Test Methods and Rate Predictions

Direct ionization from low energy protons is shown to cause upsets in a 65-nm bulk CMOS SRAM, consistent with results reported for other deep submicron technologies. The experimental data are used to calibrate a Monte Carlo rate prediction model, which is used to evaluate the importance of this upset mechanism in typical space environments. For the ISS orbit and a geosynchronous (worst day) orbit, direct ionization from protons is a major contributor to the total error rate, but for a geosynchronous (solar min) orbit, the proton flux is too low to cause a significant number of events. The implications of these results for hardness assurance are discussed.

Multiple-Bit Upset in 130 nm CMOS Technology

The probability of proton-induced multiple-bit upset (MBU) has increased in highly-scaled technologies because device dimensions are small relative to particle event track size. Both proton-induced single event upset (SEU) and MBU responses have been shown to vary with angle and energy for certain technologies. This work analyzes SEU and MBU in a 130 nm CMOS SRAM in which the single-event response shows a strong dependence on the angle of proton incidence. Current proton testing methods do not account for device orientation relative to the proton beam and, subsequently, error rate prediction assumes no angular dependencies. Proton-induced MBU is expected to increase as integrated circuits continue to scale into the deep sub-micron regime. Consequently, the application of current testing methods will lead to an incorrect prediction of error rates

Impact of Ion Energy and Species on Single Event Effects Analysis

Experimental evidence and Monte-Carlo simulations for several technologies show that accurate SEE response predictions depend on a detailed description of the variability of radiation events (e.g., nuclear reactions), as opposed to the classical single-valued LET parameter. Rate predictions conducted with this simulation framework exhibit excellent agreement with the average observed SEU rate on NASAs MESSENGER mission to Mercury, while a prediction from the traditional IRPP method, which does not include the contribution from ion-ion reactions, falls well below the observed rate. While rate predictions depend on availability of technology information, the approach described here is sufficiently flexible that reasonably accurate results describing the response to irradiation can be obtained even in the absence of detailed information about the device geometry and fabrication process.

Muon-Induced Single Event Upsets in Deep-Submicron Technology

Experimental data are presented that show low-energy muons are able to cause single event upsets in 65 nm, 45 nm, and 40 nm CMOS SRAMs. Energy deposition measurements using a surface barrier detector are presented to characterize the kinetic energy spectra produced by the M20B surface muon beam at TRIUMF. A Geant4 application is used to simulate the beam and estimate the energy spectra incident on the memories. Results indicate that the sensitivity to this mechanism will increase for scaled technologies.

Device-Orientation Effects on Multiple-Bit Upset in 65 nm SRAMs

The effects of device orientation on heavy ion-induced multiple-bit upset (MBU) in 65 nm SRAMs are examined. The MBU response is shown to depend on the orientation of the device during irradiation. The response depends on the direction of the incident ion to the n- and p-wells of the SRAM. The MBU response is simulated using Monte Carlo methods for a space environment. The probability is calculated for event size. Single-bit upsets in the space environment account for 90% of all events with exponentially decreasing probabilities of larger MBU events.

An Investigation of Dose Rate and Source Dependent Effects in 200 GHz SiGe HBTs

We present an investigation of the observed variations in the total dose tolerance of the emitter-base spacer and shallow trench isolation oxides in a commercial 200 GHz SiGe HBT technology. Proton, gamma, and X-ray irradiations at varying dose rates are found to produce drastically different degradation signatures at the various oxide interfaces. Extraction and analysis of the radiation-induced excess base current, as well as low-frequency noise, are used to probe the underlying physical mechanisms. Two-dimensional calibrated device simulations are employed to correlate the observed results to the spatial distributions of carrier recombination in forward- and inverse-mode operation for both pre- and post-irradiation levels. Possible explanations of our observations are offered and the implications for hardness assurance testing are discussed

Substrate Engineering Concepts to Mitigate Charge Collection in Deep Trench Isolation Technologies

Delayed charge collection from ionizing events outside the deep trench can increase the SEU cross section in deep trench isolation technologies. Microbeam test data and device simulations demonstrate how this adverse effect can be mitigated through substrate engineering techniques. The addition of a heavily doped p-type charge-blocking buried layer in the substrate can reduce the delayed charge collection from events that occur outside the deep trench isolation by almost an order of magnitude, implying an approximately comparable reduction in the SEU cross section

32 and 45 nm Radiation-Hardened-by-Design (RHBD) SOI Latches

Single event upset (SEU) experimental heavy ion data and modeling results for CMOS, silicon-on-insulator (SOI), 32 nm and 45 nm stacked and DICE latches are presented. Novel data analysis is shown to be important for hardness assurance where Monte Carlo modeling with a realistic heavy ion track structure, along with a new visualization aid (the Angular Dependent Cross-section Distribution, ADCD), allows one to quickly assess the improvements, or limitations, of a particular latch design. It was found to be an effective technique for making SEU predictions for alternative 32 nm SOI latch layouts.

Predicting Thermal Neutron-Induced Soft Errors in Static Memories Using TCAD and Physics-Based Monte Carlo Simulation Tools

A combination of commercial simulation tools and custom applications utilizing Geant4 physics libraries is used to analyze thermal neutron induced soft error rates in a commercial bulk CMOS SRAM. Detailed descriptions of the sensitive regions based upon technology in computer-aided design calibration are used in conjunction with a physics-based Monte Carlo simulator to predict neutron soft error cross sections that are in good agreement with experimental results