Mark R. Friendlich

Effectiveness of Internal Versus External SEU Scrubbing Mitigation Strategies in a Xilinx FPGA: Design, Test, and Analysis

A comparison of two scrubbing mitigation schemes for Xilinx field programmable gate array devices is presented. The design of the scrubbers is briefly discussed along with an examination of mitigation limitations. Heavy ion data are then presented and analyzed.

Single-Event Upsets and Multiple-Bit Upsets on a 45 nm SOI SRAM

Experimental results are presented on single-bit-upsets (SBU) and multiple-bit-upsets (MBU) on a 45 nm SOI SRAM. The accelerated testing results show the SBU-per-bit cross section is relatively constant with technology scaling but the MBU cross section is increasing. The MBU data show the importance of acquiring and analyzing the data with respect to the location of the multiple-bit upsets since the relative location of the cells is important in determining which MBU upsets can be corrected with error correcting code (ECC) circuits. For the SOI SRAMs, a large MBU orientation effect is observed with most of the MBU events occurring along the same SRAM bit-line; allowing ECC circuits to correct most of these MBU events.

Impact of Low-Energy Proton Induced Upsets on Test Methods and Rate Predictions

Direct ionization from low energy protons is shown to cause upsets in a 65-nm bulk CMOS SRAM, consistent with results reported for other deep submicron technologies. The experimental data are used to calibrate a Monte Carlo rate prediction model, which is used to evaluate the importance of this upset mechanism in typical space environments. For the ISS orbit and a geosynchronous (worst day) orbit, direct ionization from protons is a major contributor to the total error rate, but for a geosynchronous (solar min) orbit, the proton flux is too low to cause a significant number of events. The implications of these results for hardness assurance are discussed.

Low Energy Proton Single-Event-Upset Test Results on 65 nm SOI SRAM

Experimental results are presented on proton induced single-event-upsets (SEU) on a 65 nm silicon-on-insulator (SOI) SRAM. The low energy proton SEU results are very different for the 65 nm SRAM as compared with SRAMs fabricated in previous technology generations. Specifically, no upset threshold is observed as the proton energy is decreased down to 1 MeV; and a sharp rise in the upset cross-section is observed below 1 MeV. The increase below 1 MeV is attributed to upsets caused by direct ionization from the low energy protons. The implications of the low energy proton upsets are discussed for space applications of 65 nm SRAMs; and the implications for radiation assurance testing are also discussed.

SEE and TID Characterization of an Advanced Commercial 2Gbit NAND Flash Nonvolatile Memory

An advanced commercial 2Gbit NAND flash memory (90 nm technology, one bit/cell) has been characterized for TID and heavy ion SEE. Results are qualitatively similar to previous flash results in most respects, but we also detected a new dynamic failure mode

Characterizing SRAM Single Event Upset in Terms of Single and Multiple Node Charge Collection

A well-collapse source-injection mode for SRAM SEU is demonstrated through TCAD modeling. The recovery of the SRAMs state is shown to be based upon the resistive path from the p+ -sources in the SRAM to the well. Multiple cell upset patterns for direct charge collection and the well-collapse source-injection mechanisms are predicted and compared to SRAM test data.

Device-Orientation Effects on Multiple-Bit Upset in 65 nm SRAMs

The effects of device orientation on heavy ion-induced multiple-bit upset (MBU) in 65 nm SRAMs are examined. The MBU response is shown to depend on the orientation of the device during irradiation. The response depends on the direction of the incident ion to the n- and p-wells of the SRAM. The MBU response is simulated using Monte Carlo methods for a space environment. The probability is calculated for event size. Single-bit upsets in the space environment account for 90% of all events with exponentially decreasing probabilities of larger MBU events.

Compendium of Current Single Event Effects Results for Candidate Spacecraft Electronics for NASA

Sensitivity of a variety of candidate spacecraft electronics to proton and heavy ion induced single event effects is presented. Devices tested include digital, linear, and hybrid devices.

An Analysis of Single Event Upset Dependencies on High Frequency and Architectural Implementations within Actel RTAX-S Family Field Programmable Gate Arrays

In order to investigate frequency and architectural effects on Single Event Upset cross sections within RTAX-S FPGA devices, a novel approach to high speed testing is implemented. Testing was performed at variable speeds ranging from 15 MHz to 150 MHz

32 and 45 nm Radiation-Hardened-by-Design (RHBD) SOI Latches

Single event upset (SEU) experimental heavy ion data and modeling results for CMOS, silicon-on-insulator (SOI), 32 nm and 45 nm stacked and DICE latches are presented. Novel data analysis is shown to be important for hardness assurance where Monte Carlo modeling with a realistic heavy ion track structure, along with a new visualization aid (the Angular Dependent Cross-section Distribution, ADCD), allows one to quickly assess the improvements, or limitations, of a particular latch design. It was found to be an effective technique for making SEU predictions for alternative 32 nm SOI latch layouts.