Kevin M. Warren

Simultaneous single event charge sharing and parasitic bipolar conduction in a highly-scaled SRAM design

A novel mechanism for upset is seen in a commercially available 0.25 /spl mu/m 10-T SEE hardened SRAM cell. Unlike traditional multiple node charge collection in which diffusions near a single event strike collect the deposited carriers, this new mechanism involves direct drift-diffusion collection at an NFET transistor in conjunction with parasitic bipolar conduction in nearby PFET transistors. The charge collection with the parasitic bipolar conduction compromise the SEE hardened design, thus causing upsets. The mechanism was identified using laser testing and three-dimensional TCAD simulations.

The contribution of nuclear reactions to heavy ion single event upset cross-section measurements in a high-density SEU hardened SRAM

Heavy ion irradiation was simulated using a Geant4 based Monte-Carlo transport code. Electronic and nuclear physics were used to generate statistical profiles of charge deposition in the sensitive volume of an SEU hardened SRAM. Simulation results show that materials external to the sensitive volume can affect the experimentally measured cross-section curve.

Monte Carlo Simulation of Single Event Effects

In this paper, we describe a Monte Carlo approach for estimating the frequency and character of single event effects based on a combination of physical modeling of discrete radiation events, device simulations to estimate charge transport and collection, and circuit simulations to determine the effect of the collected charge. A mathematical analysis of the procedure reveals it to be closely related to the rectangular parallelepiped (RPP) rate prediction method. The results of these simulations show that event-to-event variation may have a significant impact when predicting the single-event rate in advanced spacecraft electronics. Specific criteria for supplementing established RPP-based single event analysis with Monte Carlo computations are discussed.

Impact of Low-Energy Proton Induced Upsets on Test Methods and Rate Predictions

Direct ionization from low energy protons is shown to cause upsets in a 65-nm bulk CMOS SRAM, consistent with results reported for other deep submicron technologies. The experimental data are used to calibrate a Monte Carlo rate prediction model, which is used to evaluate the importance of this upset mechanism in typical space environments. For the ISS orbit and a geosynchronous (worst day) orbit, direct ionization from protons is a major contributor to the total error rate, but for a geosynchronous (solar min) orbit, the proton flux is too low to cause a significant number of events. The implications of these results for hardness assurance are discussed.

Analysis of Parasitic PNP Bipolar Transistor Mitigation Using Well Contacts in 130 nm and 90 nm CMOS Technology

Three-dimensional TCAD models are used in mixed- mode simulations to analyze the effectiveness of well contacts at mitigating parasitic PNP bipolar conduction due to a direct hit ion strike. 130 nm and 90 nm technology are simulated. Results show careful well contact design can improve mitigation. However, well contact effectiveness is seen to decrease from the 130 nm to the 90 nm simulations.

Impact of Ion Energy and Species on Single Event Effects Analysis

Experimental evidence and Monte-Carlo simulations for several technologies show that accurate SEE response predictions depend on a detailed description of the variability of radiation events (e.g., nuclear reactions), as opposed to the classical single-valued LET parameter. Rate predictions conducted with this simulation framework exhibit excellent agreement with the average observed SEU rate on NASAs MESSENGER mission to Mercury, while a prediction from the traditional IRPP method, which does not include the contribution from ion-ion reactions, falls well below the observed rate. While rate predictions depend on availability of technology information, the approach described here is sufficiently flexible that reasonably accurate results describing the response to irradiation can be obtained even in the absence of detailed information about the device geometry and fabrication process.

Role of heavy-ion nuclear reactions in determining on-orbit single event error rates

Simulations show that neglecting ion-ion interaction processes (both particles having Z>1) results in an underestimation of the total on-orbit single event upset error rate by more than two orders of magnitude for certain technologies. The inclusion of ion-ion nuclear reactions leads to dramatically different SEU error rates for CMOS devices containing high Z materials compared with direct ionization by the primary ion alone. Device geometry and material composition have a dramatic effect on charge deposition in small sensitive volumes for the spectrum of ion energies found in space, compared with the limited range of energies typical of ground tests.

Impact of Heavy Ion Energy and Nuclear Interactions on Single-Event Upset and Latchup in Integrated Circuits

The effects of heavy ion energy and nuclear interactions on the single-event upset (SEU) and single-event latchup (SEL) response of commercial and radiation-hardened CMOS ICs are explored. Above the threshold LET for direct ionization-induced upsets, little difference is observed in single-event upset and latchup cross sections measured using low versus high energy heavy ions. However, significant differences between low- and high-energy heavy ion test results are observed below the threshold LET for single-node direct ionization-induced upsets. The data suggest that secondary particles produced by nuclear interactions play a role in determining the SEU and SEL hardness of integrated circuits, especially at low LET. The role of nuclear interactions and implications for radiation hardness assurance and rate prediction are discussed.

Characterizing SRAM Single Event Upset in Terms of Single and Multiple Node Charge Collection

A well-collapse source-injection mode for SRAM SEU is demonstrated through TCAD modeling. The recovery of the SRAMs state is shown to be based upon the resistive path from the p+ -sources in the SRAM to the well. Multiple cell upset patterns for direct charge collection and the well-collapse source-injection mechanisms are predicted and compared to SRAM test data.

Application of RADSAFE to Model the Single Event Upset Response of a 0.25

The RADSAFE simulation framework is described and applied to model SEU in a 0.25 mum CMOS 4 Mbit SRAM. For this circuit, the RADSAFE approach produces trends similar to those expected from classical rectangular parallelepiped models, but more closely represents the physical mechanisms responsible for SEU in the SRAM circuit.