S. Lipa

Multi-gigahertz low-power low-skew rotary clock scheme

On-chip clock frequencies in the gigaHertz range require generators with low skew and low jitter to avoid timing problems. This rotary clock distribution architecture provides low-skew low-jitter, gigaHertz-rate clocking with high edge rates and low power consumption, works over a wide power supply range and is completely scalable. The frequency is limited only by f/sub T/ of the integrated circuit technology used; an f/sub T/ of approximately 30 GHz produces square waves with 20 ps transition times. In addition, there is no limit to the size of the chip that can be clocked, and both multiphase and non-overlapping noise-immune differential clocking are supported.

The development of a macro-modeling tool to develop IBIS models

A tool to convert SPICE netlists to IBIS (Input/Output Buffer Information Specification) models is presented. This tool simulates the netlist on a user-desirable SPICE engine and produces both static and dynamic characteristics of the IBIS model.

Design for 3D Integration and Applications

3D stacking and integration can provide system advantages equivalent to up to two technology nodes of scaling. This paper explores application drivers and computer aided design (CAD) for 3D ICs.

Crosstalk driven routing advice

This paper examines the feasibility of generating routing advice for interconnects on printed circuit boards (PCBs) at the design stage, on the basis of crosstalk noise requirements and relevant timing information. A set of analytical expressions have been developed to relate physical design parameters, such as the spacing between a pair of coupled signal lines, to the amount of crosstalk noise generated on these lines. Timing windows have been used to define time intervals during which noise on a specific signal line can affect the functioning of the entire system. An algorithm has been developed, based on the above expressions, to estimate the minimum safe spacing between a pair of coupled signal lines, given the crosstalk noise budget and timing information.<<ETX>>

Comparison of methods for determining the capacitance of planar transmission lines with application to multichip module characterization

The techiques for determining the capacitance of embedded interconnects in an MCM-D MCM (multichip module) are compared. The error is estimating this capacitance in generally the greatest contributor to the overall error in determining the impedance of interconnects and discontinuities. Using in situ calibration microwave characterization of various MCM interconnects fabricated using an alumina on polyimide MCM-D process is reported. >

Experimental characterization of transmission lines in thin-film multichip modules

Signal propagation on transmission lines fabricated in thin polyimide films on silicon substrates is investigated. Series resistive and shunt conductive losses are separated and it is shown that the effective dielectric loss is much higher than that expected from bulk material properties.

Experimental electrical characterization of on-chip interconnects

This paper describes the transmission line and capacitance measurements made on a 0.25 micron test chip. Transmission lines were characterized to frequencies up to 20 GHz using a Hewlett Packard network analyzer and capacitances were determined using conventional capacitance meter. These measurements will help to develop benchmark capacitance and resistance values of on-chip interconnect structures. Measurements of the physical dimension of the interconnect structures will facilitate the determination of the effects of geometric assumptions made by capacitance extraction tools.

Experimental characterization of interconnects and discontinuities in thin-film multichip module substrates

Interconnects and discontinuities in a thin-film multichip module substrate are experimentally characterized, taking into account the effective dielectric loss attributed to dielectric anisotropy of the thin-film.<<ETX>>

Flip-chip power distribution

By using thin-film (MCM-D) and flip-chip solder bump technologies to distribute power and ground to an IC, the percentage of metal fill required on the power and ground layers can be reduced. However, significant reductions require a very dense solder bump technology.

Issues in chip-package codesign with MCM-D/flip-chip technology

By distributing on-chip global power, ground, and clock planes on a thin film MCM, the IC can be made smaller, faster, and less noisy while consuming less power. These advantages are demonstrated by a number of case studies: two demonstrator ICs and an analysis of the DEC Alpha 21264 clock distribution scheme. However, there are a number of practical issues that need to be addressed, including process variations and test. In this paper, we present the case studies and a treatment of these practical issues.