Toby Schaffer

Issues in partitioning integrated circuits for MCM-D/flip-chip technology

In order to successfully partition a high performance large monolithic chip onto MCM-D/flip-chip-solder-bump technology, a number of key issues must be addressed. These include the following: (1) Partitioning a single clock-cycle path across the chip boundary within using; (2) Ability to use off-the-shelf memories; (3) Using the MCM for power, ground, and clock distribution; and (4) Managing test costs. This paper presents a discussion on these issues, using a CPU as an example, and speculates on some interesting possibilities arising from partitioning.

A flip-chip implementation of the Data Encryption Standard (DES)

We describe a flip-chip MCM-D implementation of a Data Encryption Standard (DES) engine. Novel features include the following: use of dense area-array I/O to achieve high bandwidth, fully-pipelined architecture which supports multiple encryptions (e.g., triple DES) with no loss of throughput; ability to multiplex datastreams, each under the control of a potentially unique key, and use of the MCM-D substrate to distribute power, ground and clock signals. The chip is being fabricated in a 0.6 /spl mu/m CMOS process, while the MCM is being built in a 4-layer polyimide MCM-D process. Circuit simulations indicate the device will operate with a throughput of 9.6 Gb/s.

Infrastructure and course progression for complex IC design education

The ability to cope with design complexity is an important skill for computer engineers, especially potential system on a chip design engineers. Complexity has many facets, including gate count, the ability to handle multiple disciplines simultaneously, and the ability to cope with complex CAD tools. Teaching complexity also requires considerable investment in tool flows, design examples and tutorials. Here, the approach used at North Carolina State University, USA, is described and illustrated.

A technique for high-speed, fine-resolution pattern generation and its CMOS implementation

This paper presents an architecture for generating a high-speed data pattern with precise edge placement (resolution) by using the matched delay technique. The technique involves passing clock and data signals through arrays of matched delay elements in such a way that the data rate and resolution of the generated data stream are controlled by the difference of these matched delays. This difference can be made much smaller than an absolute gate delay. Since the resolution of conventional designs is determined by these absolute delays, the matched delay technique yields a much finer resolution than traditional methods and, in addition, generates high data rate patterns without the need of a high-speed clock. The matched delay technique lends itself to high-precision and high-speed applications such as fast network interfaces or test pattern generators. This paper also describes a matched delay data generator submitted for fabrication in a MOSIS 1.2 /spl mu/m CMOS technology. This implementation used biased delay elements to internally compensate for temperature and process variations. Simulations indicate the implementation described in this paper can generate data signals with on-chip bit rates of 833 Mb/s and resolutions of 100 ps.

Issues in chip-package codesign with MCM-D/flip-chip technology

By distributing on-chip global power, ground, and clock planes on a thin film MCM, the IC can be made smaller, faster, and less noisy while consuming less power. These advantages are demonstrated by a number of case studies: two demonstrator ICs and an analysis of the DEC Alpha 21264 clock distribution scheme. However, there are a number of practical issues that need to be addressed, including process variations and test. In this paper, we present the case studies and a treatment of these practical issues.

High speed, fine resolution pattern generation using the matched delay technique

This paper presents an architecture for generating a high-speed data pattern with precise edge placement (resolution) by using the matched delay technique. The technique involves passing clock and data signals through arrays of matched delay elements in such a way that the data rate and resolution of the generated data stream are controlled by the difference of these matched delays. This difference can be made much smaller than an absolute gate delay. Since the resolution of conventional designs is determined by these absolute delays, the matched delay technique yields a much finer resolution as well as higher speeds than traditional methods. The matched delay technique lends itself to high-precision and high-speed applications such as fast network interfaces or test pattern generators. This paper also describes a matched delay data generator submitted for fabrication in a MOSIS 1.2 /spl mu/m CMOS technology. Simulations indicate that data signals with on-chip bit rates of 833 Mb/s and resolutions of 100 ps can be generated.