Alberto Cestero

Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips

Electrical fuse (eFUSE) has become a popular choice to enable memory redundancy, chip identification and authentication, analog device trimming, and other applications. We will review the evolution and applications of electrical fuse solutions for 180 nm to 45 nm technologies at IBM, and provide some insight into future uses in 32 nm technology and beyond with the eFUSE as a building block for the autonomic chip of the future.

A Compact eFUSE Programmable Array Memory for SOI CMOS

Demonstrating a >10X density increase over traditional VLSI fuse circuits, a compact eFUSE programmable array memory configured as a 4 Kb one-time programmable ROM (OTPROM) is presented using a 6.2 mum2 NiSix silicide electromigration ITIR cell in 65 nm SOI CMOS. A 20 mus programming time at 1.5 V is achieved by asymmetrical scaling of the fuse and a shared differential sensing scheme. Having zero process cost adder, eFUSE is fully compatible with standard VLSI manufacturing.

An 800-MHz embedded DRAM with a concurrent refresh mode

An 800-MHz embedded DRAM macro employs a memory cell utilizing a device from the 90-nm high-performance technology menu; a 2.2-nm gate oxide 1.5 V IO device. A concurrent refresh mode is designed to improve the memory utilization to over 99% for a 64 /spl mu/s data retention time. A concurrent refresh scheduler utilizes up-count and down-count registers to identify at least one array to be refreshed at every clock cycle, emulating a classical distributed refresh mode. A command multiplier employs low frequency phased clock signals to generate the clock, commands, and addresses at rates up to 4/spl times/ that of the tester frequency. The macro integrates masked redundancy allocation logic during at speed multibank test. The hardware results show a 312-MHz random access frequency and 800-MHz multibank frequency at 1.2 V, respectively.

Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM

A random intrinsic chip ID generation method using retention fails is implemented in 32 nm SOI embedded DRAM. A dynamic key algorithm employs a unique pair of 4 Kb binary strings for an ID record for secure authentication. These strings are generated by controlling a wordline low voltage to search for a number of fails matching the corresponding challenge numbers. The algorithm further includes field-tolerant authentication by detecting a number of common bits analytically guaranteed for successful recognition, while preventing ID spoofing during the read operation. This results in 100% successful unique ID generation and recognition in two temperature and three voltage conditions per chip for a total of ~ 420 k ID pair comparisons in 266 chips. The analytical model predicts a 99.999% successful recognition rate for 106 parts. Finally, a method to enable a field-tolerant ID using multiple domains will be discussed.

A Self-Authenticating Chip Architecture Using an Intrinsic Fingerprint of Embedded DRAM

An architecture for enabling self-authenticating chips uses 4 Kb electrically programmable fuses (eFUSE) to store bit strings representing encrypted intrinsic fingerprints obtained by offset-superimposing six out of one thousand 4 Kb domains randomly chosen in 4 Mb embedded DRAM. Authentication is accomplished by regenerating various encrypted intrinsic fingerprints, which are then compared with the bit strings in the eFUSE. Monte Carlo simulations demonstrate that, targeting an average of 32 retention fails per domain, the strings are unique and authentication is statistically guaranteed without bit correction even when unstable bits are introduced. The preliminary results are confirmed in > 50 parts containing 4 Mb memory implemented in 22-nm SOI hardware under the target voltage ±10% conditions. The analytical model predicts > 10 20 years to crack the encryption by brute force, while satisfying > 99.9999% successful authentication for one million parts.

A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access

A 1.1 Mb embedded DRAM macro (eDRAM), for next-generation IBM SOI processors, employs 14 nm FinFET logic technology with 0.0174 μm2 deep-trench capacitor cell. A Gated-feedback sense amplifier enables a high voltage gain of a power-gated inverter at mid-level input voltage, while supporting 66 cells per local bit-line. A dynamic-and-gate-thin-oxide word-line driver that tracks standard logic process variation improves the eDRAM array performance with reduced area. The 1.1 Mb macro composed of 8 ×2 72 Kb subarrays is organized with a center interface block architecture, allowing 1 ns access latency and 1 ns bank interleaving operation using two banks, each having 2 ns random access cycle. 5 GHz operation has been demonstrated in a system prototype, which includes 6 instances of 1.1 Mb eDRAM macros, integrated with an array-built-in-self-test engine, phase-locked loop (PLL), and word-line high and word-line low voltage generators. The advantage of the 14 nm FinFET array over the 22 nm array was confirmed using direct tester control of the 1.1 Mb eDRAM macros integrated in 16 Mb inline monitor.

80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity

An 80Kb logic Embedded Multi-Time Programmable Memory (MTPM) employs charge trapping and de-trapping behavior in 32nm/22nm High-K transistor, resulting in no added process complexity. Multi-step verification with overwrite protection employs block-write and signal margin degradation (~30%) to satisfy 10 year retention at 105° C.

Dynamic intrinsic chip ID using 32nm high-K/metal gate SOI embedded DRAM

A random intrinsic chip ID method generates a pair of 4Kb binary strings using retention fails in 32nm SOI embedded DRAM. Hardware results show ID overlap distance mean=0.58 and σ=0.76 and demonstrate 100% authentication for 346 chips. The analytical model predicts >; 99.999% unique IDs for 106 parts.

3Di DC-DC Buck Micro Converter with TSVs, Grind Side Inductors, and Deep Trench Decoupling Capacitors in 32nm SOI CMOS

High performance processors and ASICs typically require multiple voltages and multi-domain voltage controls across the die. Conventional approaches distribute the voltage regulation elements between the processor, the package laminate, and the printed circuit board. We propose an alternative approach where the voltage regulator is embodied in a 3D configuration such that the inductor, capacitor and the switches are formed on a separate silicon chip sandwiched between the processor and the laminate. Due to the close proximity of regulator to the processor, this approach can enable granular voltage domains, while minimizing disruptions to the processor layout. We describe a 4-f DC-DC buck converter fabricated on 32nm SOI wafers using TSVs to connect the switches on the front-side of the wafer to the inductors on the grind-side. The process builds on a 32nm SOI CMOS flow, adding deep trench (DT) capacitors and TSVs. Down conversion from a standard I/O voltage under various load conditions was evaluated, and an efficiency of 77% was achieved.

80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity

This paper describes the design and implementation of an 80-kb logic-embedded non-volatile multi-time programmable memory (MTPM) with no added process complexity. Charge trap transistors (CTTs) that exploit charge trapping and de-trapping behavior in high-K dielectric of 32-/22-nm Logic FETs are used as storage elements with logic-compatible programming voltages. A high-gain slew-sense amplifier (SA) is used to efficiently detect the threshold voltage difference (