John M. Safran

Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips

Electrical fuse (eFUSE) has become a popular choice to enable memory redundancy, chip identification and authentication, analog device trimming, and other applications. We will review the evolution and applications of electrical fuse solutions for 180 nm to 45 nm technologies at IBM, and provide some insight into future uses in 32 nm technology and beyond with the eFUSE as a building block for the autonomic chip of the future.

3D copper TSV integration, testing and reliability

Node-agnostic Cu TSVs integrated with high-K/metal gate and embedded DRAM were used in functional 3D modules. Thermal cycling and stress results show no degradation of TSV or BEOL structures, and device and functional data indicate that there is no significant impact from TSV processing and/or proximity.

A Compact eFUSE Programmable Array Memory for SOI CMOS

Demonstrating a >10X density increase over traditional VLSI fuse circuits, a compact eFUSE programmable array memory configured as a 4 Kb one-time programmable ROM (OTPROM) is presented using a 6.2 mum2 NiSix silicide electromigration ITIR cell in 65 nm SOI CMOS. A 20 mus programming time at 1.5 V is achieved by asymmetrical scaling of the fuse and a shared differential sensing scheme. Having zero process cost adder, eFUSE is fully compatible with standard VLSI manufacturing.

Reliability Qualification of CoSi2 Electrical Fuse for 90Nm Technology

The reliability of CoSi2/p-poly Si electrical fuse (eFUSE) programmed by electromigration for 90nm technology will be presented. Both programmed and unprogrammed fuse elements were shown to be stable through extensive reliability evaluations. A qualification methodology is demonstrated to define an optimized reliable electrical fuse programming window by combining fuse resistance measurements, physical analysis, and functional sensing data. This methodology addresses the impact on electrical fuse reliability caused by process variation and device degradation (e.g., NBTI) in the sensing circuit and allows an adequate margin to ensure electrical fuse reliability over the chip lifetime

Reliability investigation of NiPtSi electrical fuse with different programming mechanisms

The reliability of NiPtSi/p-poly Si electrical fuses with different programming mechanisms, i.e., electromigration and thermal rupture, was investigated in terms of fuse resistance stability and fuse array functionality for the 65-nm technology node. The resistance of the fuses programmed within the electromigration programming window was found to be very stable; resistance shift was only observed on fuses programmed in the underprogrammed mode, which results in incomplete electromigration. For fuses programmed with the thermal rupture mechanism, both resistance shift and functional sensing fails were observed. Furthermore, a guard band was defined for fuses programmed with an electromigration mechanism to ensure sufficient margins for fuse reliability. However, a guard band cannot be defined for fuses programmed with a rupture mode due to the unpredictable nature of the rupture programming mechanism. The unprogrammed fuse elements were shown to be stable through extensive reliability evaluations.

A power-optimized widely-tunable 5-GHz monolithic VCO in a digital SOI CMOS technology. On high resistivity substrate

This paper describes the design and technology optimization of power-efficient monolithic VCOs with wide tuning range. Four 5-GHz LC-tank VCOs were fabricated in a 0.12-μm SOI CMOS technology that was not enhanced for RF applications. High and regular resistivity substrates were used, as were single-layer and multiple-layer copper inductors. Using a new figure-of-merit (FOMT) that encompasses power dissipation, phase noise and tuning range, our best VCO has an FOMT of -189 dBc/Hz. The measured frequency tuning range is 22 % and the phase noise is -126 dBc/Hz at 1 MHz offset for 4.5-GHz. Oscillation was achieved at 5.4-GHz at a minimum power consumption of 500 μW.

Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM

A random intrinsic chip ID generation method using retention fails is implemented in 32 nm SOI embedded DRAM. A dynamic key algorithm employs a unique pair of 4 Kb binary strings for an ID record for secure authentication. These strings are generated by controlling a wordline low voltage to search for a number of fails matching the corresponding challenge numbers. The algorithm further includes field-tolerant authentication by detecting a number of common bits analytically guaranteed for successful recognition, while preventing ID spoofing during the read operation. This results in 100% successful unique ID generation and recognition in two temperature and three voltage conditions per chip for a total of ~ 420 k ID pair comparisons in 266 chips. The analytical model predicts a 99.999% successful recognition rate for 106 parts. Finally, a method to enable a field-tolerant ID using multiple domains will be discussed.

A Commercial Field-Programmable Dense eFUSE Array Memory with 99.999% Sense Yield for 45nm SOI CMOS

This paper describes a second-generation one-time programmable read-only memory (OTPROM) that provides these features through a balanced bitline, resistor pull-up, differential sense amp with a programmable reference.

A 12dBm 320GHz GBW distributed amplifier in a 0.12/spl mu/m SOI CMOS

This paper describes a 9-stage distributed amplifier which achieves 11 dB gain and 90 GHz 3dB cut-off frequency, equivalent to a 320 GHz GBW. The measured 1 dB output compression point is 12 dBm at 20 GHz, the OIP3 is 15.5 dBm at 50 GHz, and the noise figure is 5.5 dB at 18 GHz.

Through silicon via (TSV) effects on devices in close proximity - the role of mobile ion penetration - characterization and mitigation

A new interaction between TSV processes and devices in close proximity, different from mechanical stress, is identified, studied and mitigated. Detailed characterization via Triangular Voltage Sweep (TVS) and SIMS shows the role of mobile ion penetration from BEOL layers. An improved process is presented and confirmed in test structures and DRAM.