Albrecht Kieslich

Stacked via with specially designed landing pad for integrated semiconductor structures

Method for fabricating a semiconductor product with a memory area and a logic area

Method for fabricating a microelectronic structure

Method for planarizing an isolating layer

Method for producing an insulation

Mask for fabricating semiconductor components

Method for fabricating through-holes with different sizes e.g. for integrated circuit, requires use of auxiliary layer for generating different structural sizes

Method of forming a bitline and a bitline contact, and dynamic memory cell including a bitline and bitline made contact according to the method

Compact semiconductor structure

Patterning of content areas in multilayer metalization configurations of semiconductor components