Aldo Pena Perez

Slew-rate and gain enhancement in two stage operational amplifiers

A two stage op-amp with an effective technique to enhance slew-rate and gain is presented. The enhancement is provided by an auxiliary monitor circuit which is activated in slewing conditions, but can contribute to the gain in normal conditions. The amplifier, simulated in a 0.18 µm technology, achieves 74 dB DC gain, 160 MHz bandwidth and 26.8 V/µs slew-rate for a load capacitance of 1.75 pF with 362 µW power consumption, considering a supply voltage of 1.8 V.

A 84dB SNDR 100kHz bandwidth low-power single op-amp third-order ΔΣ modulator consuming 140μW

This third-order ΔΣ modulator [1, 2], suitable for high-resolution low-power sensor systems, consumes 140μW to obtain 84dB SNDR with OSR=16 and 100kHz signal bandwidth. The achieved FoM is 54fJ/conversion-step

Third-order ΣΔ modulator with 61-dB SNR and 6-MHz bandwidth consuming 6 mW

This low-power sigma-delta modulator targets the DVB-H requirements and achieves about 10 bit with 6-MHz signal band and a FoM of 0.59 pJ/conversion. The used scheme is a multi-bit third order modulator that, with suitable topological modification, enables using two op-amps and enjoying a swing reduction at the quantizer input. The area of the circuit, fabricated with a 0.18-mum analog CMOS technology, is 0.32 mum2. The nominal supply voltage is 1.8 V and the clock frequency is 96 MHz (OSR = 8). Experimental measurements confirm the behavioral study made accounting for the op-amps limitations.

Performance enhanced op-amp for 65nm CMOS technologies and below

Multistage operational amplifiers suitable for nanometer-scale CMOS technologies and low-voltage applications are described. The low intrinsic gain of transistors is compensated for with cascade of single-stage amplifiers. Techniques for compensations are revisited and the optimal solution identified. An example of a novel scheme that achieves 67 dB of DC gain, 320 MHz of bandwidth and 61 degrees of phase margin is presented. The power consumption is as low as 0.24 mW with a slew rate of 84.5 V/μ s. The CMOS technology is 65 nm; the design uses only minimum channel length transistors.

ΔΣ time interleaved current steering DAC with dynamic elements matching

The architecture for very-high speed DAC with medium oversampling and high resolution is discussed. The scheme uses an hybrid sigma-delta scheme that processes LSBs of the input word and obtain digital to analog conversion with an hybrid current steering DAC with dynamic element matching of MSBs and time interleaved conversion of LSBs. The return-to-zero for all elements ensures the required linearity of the analog output. Computer simulations verify the benefit of the scheme.

ΣΔ Modulator with op-amp gain compensation for nanometer CMOS technologies

A gain compensated op-amp for discrete-time ΣΔ modulators is described. The method greatly reduces the integrators phase error caused by low DC gain on amplifiers. The scheme uses an additional unity gain buffer to correct the error caused by gains as low as 20 dB, thus enabling high-performance ΣΔ modulators in nanometer-scale CMOS technologies. Design strategies for op-amps and buffer designed with a 65 nm technology to be used with the method are considered. The effectiveness of the approach is verified with a second-order ΣΔ modulator simulated at behavioral level with MATLAB and Verilog-A descriptions. The low sensitivity to buffer gains variations is also verified.

An incremental ADC sensor interface with input switch-Less integrator featuring 220-nV rms resolution with ±30-mV input range

An incremental ADC for Wheatstone CMOS stress sensor systems is described. A switched-capacitors integrator without switches toward virtual ground avoids spur signals, clock feed-through, residual offset and glitches. The circuit, fabricated in a 0.35-μm CMOS technology, consumes 42 μW at 500-kHz clock and 2.8-V supply. Low speed chopping cancels offset and limits the 1/f noise contribution. The signal-to-noise ratio with measures lasting 220 periods is 114 dB at ±100 mV full-scale range. The active area is 0.32 mm2.

Use of time variant digital sigma-delta for fractional frequency synthesizers

This paper proposes a new low order time variant digital ΣΔ MASH modulator for fractional frequency synthesizers. The phase noise spectrum is improved as the spur tones from the fractional modulation are disabled. The usage of low order time variant MASH architectures reduces the number of levels that control the programable divider, reducing therefore the complexity and power requirements of the synthesizer.

A low-power third-order ΔΣ modulator using a single operational amplifier

An architecture for low-power ΔΣ modulators suitable for high-resolution portable sensor systems is presented. The circuit uses a single operational amplifier to achieve a third-order noise shaping. The two-stage op-amp employs a boosting technique that increases by 5 the slew-rate. The circuit, simulated at the transistor level using a conventional 0.18-µm CMOS technology, obtains a peak SNDR of 88 dB over an input signal bandwidth of 100 kHz. The simulated power consumption is 125 µW with a 1.5-V supply voltage. The achieved Figure of Merit (FoM) is 31 fJ/conversion-level.