Alessandro Callegari

Charge trapping related threshold voltage instabilities in high permittivity gate dielectric stacks

An experimental and modeling study of charge trapping related threshold voltage shifts in Al2O3 and HfO2 n-type field effect transistors (nFET) is reported. The dependence of threshold voltage, subthreshold slope, and gate leakage currents on stressing time and injected charge carrier density are investigated as a function positive bias stress voltage and temperature. Based on experimental data, a model for trapping of charges in the existing traps is developed. The model is similar to SiO2 charge trapping models with one exception. Unlike SiO2 models, the model assumes a continuous distribution in trapping capture cross sections. The model predicts that threshold voltage would increase with a power law dependence on stressing time and injected charge carrier density (Ninj) in the initial stages of stressing. The model calculates threshold voltage shifts as a function of stress time and Ninj, thereby provides estimates of threshold voltage shifts after 10 years lifetime. It also provides insights into the...

Charge trapping in high k gate dielectric stacks

Charge trapping in Al/sub 2/O/sub 3/ and HfO/sub 2/ nFETs is studied. The dependence of threshold voltage, subthreshold slope and gate leakage currents are investigated as a function of stressing time, voltage and temperature. Based on the experimental data, a model is developed for predicting threshold voltage shifts as a function stressing time. The model is compatible with both Al/sub 2/O/sub 3/ and HfO/sub 2/ data. Using the model, threshold voltage shifts after 10 years of stressing is predicted and trapping capture cross sections are estimated. A comparison between Al/sub 2/O/sub 3/ and HfO/sub 2/ is also made.

Ion beam alignment for liquid crystal display fabrication

The ability to align liquid crystals to a substrate is a critical step in the liquid crystal display (LCD) manufacturing process with the industry standard technique employing a mechanical rubbing technique to accomplish this function. However, mechanical rubbing can result in debris generation contaminating not only the substrate being processed but also the clean room housing the equipment. As such, post-cleaning of the display panels is required to remove the debris from the surface in addition to the physical isolation of the mechanical rubbing equipment within the clean room environment introducing considerable time and expense. In addition, uneven wear of the mechanical roller during the rubbing process may result in localized defects that will not be observed until final inspection of a completely assembled display. We have developed and introduced into LCD manufacturing a non-contact alignment technique utilizing both diamond-like carbon (DLC) and a low energy ion beam (IB). The replacement of the polyimide alignment layer with DLC results in a completely dry processing technique for both the thin film deposition and alignment steps.

Optical properties of hydrogenated amorphous‐carbon film for attenuated phase‐shift mask applications

The optical properties of a plasma‐deposited amorphous‐carbon film have been investigated in the ultraviolet (365 nm) and deep ultraviolet range (248 nm). By varying process conditions, the optical transmission through the films was tuned from 4% to 20% at 365 nm and from 3% to 9% at 248 nm. This tuneability was related to the hydrogen content of the film as affected by the process parameters. The index of refraction n measured by spectroscopic ellipsometry is ∼2 at the wavelengths used. These optical properties make this film attractive for use in single layer attenuated phase‐shift masks for potential application in 0.25 μm lithography at 365 and 248 nm.

Rapid thermal diffusion and ohmic contacts using zinc in GaAs and GaAlAs

We report behavior of zinc diffusion and p‐type ohmic contacts to GaAs and GaAlAs (aluminum mole fraction ∼0.3) by Zn3As2 as vapor source and zinc embedded in tungsten films as solid source using rapid thermal processing. Tungsten acts as an inert refractory metallurgy during the processing. The diffusion profiles show high surface concentrations (mid 1019 cm−3 to low 1020 cm−3) and a diffusion profile in agreement with Tuck’s model of substitutional‐interstitial diffusion in the presence of vacancy nonequilibrium. Both GaAs and GaAlAs show excellent transport properties with mobilities of 75–100 and 40–60 cm2 V−1 s−1, respectively, at room temperature. Short‐time (sub‐12‐s) diffusions lead to sub‐1000‐A diffused contacts in the 650–900 °C temperature range with contact resistances below a measurement accuracy of 5×10−7 Ω cm2. The contact technology has been demonstrated in heterostructure bipolar transistors and p‐channel heterostructure field‐effect transistors. It is an attractive alternative to conven...

Maximized Benefit of La–Al–O Higher-

The benefit of La-Al-O higher-k gate dielectrics is maximized by optimizing the Al/(La+Al) atomic ratio. The Al/(La+Al) atomic ratio modulates the band gap, dielectric constant, and interface dipoles, resulting in change of energy band alignment. The La-Al-O film with an Al/(La+Al) atomic ratio of 0.25 yields a maximum leakage current reduction exceeding HfO2 and La2O3, owing to the optimized band alignment structure. Moreover, a SiON underlayer instead of SiO2 enables additional equivalent oxide thickness scaling down to 7.4 Å while maintaining the fully reduced leakage current with a gate-first process.

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The impact of thermal budget on La- and Al-induced dipoles is systematically investigated by femtosecond pump/probe photoelectron spectroscopy. We find that the La-induced dipole requires annealing at 300 °C for complete activation, whereas the Al-induced dipole is activated at the lower temperature but requires annealing at 300 °C to eliminate a counteracting sheet charge. When La and Al atoms coexist on a SiO2 surface, the La-induced dipole becomes dominative after a silicate-forming reaction at the temperature above 600 °C. This phenomenon is attributed to the different natures of the La- and Al-induced dipoles, i.e., long-range and short-range.

Gate Dielectrics by Optimizing the La/Al Atomic Ratio

The operation of long- and short-channel enhancement-mode In0.7Ga0.3As-channel MOSFETs with high-k gate dielectrics are demonstrated for the first time. The devices utilize an undoped buried-channel design. For a gate length of 5 mum, the long-channel devices have Vt= +0.25 V, a subthreshold slope of 150 mV/dec, an equivalent oxide thickness of 4.4 +/ - 0.3 nm, and a peak effective mobility of 1100 cm2/Vldrs. For a gate length of 260 nm, the short-channel devices have Vt=+0.5 V and a subthreshold slope of 200 mV/dec. Compared with Schottky-gated high-electron-mobility transistor devices, both long- and short-channel MOSFETs have two to four orders of magnitude lower gate leakage.

Temperature-dependent La- and Al-induced dipole behavior monitored by femtosecond pump/probe photoelectron spectroscopy

A novel LC alignment method has been developed. In this, the conventional polyimide film and cloth rubbing have been replaced by a diamond-like-carbon film and an ion beam respectively. The novel method has been used in pilot-line manufacturing to produce super high quality panels: 15″ TN mode and 22″ IPS mode. These panels will be demonstrated, and the advantage of new method will be discussed.

Enhancement-Mode Buried-Channel

The operation of long- and short-channel enhancement-mode In0.7Ga0.3As-channel MOSFETs with high-k gate dielectrics are demonstrated for the first time. The devices utilize an undoped buried-channel design. For a gate length of 5 mum, the long-channel devices have Vt= +0.25 V, a subthreshold slope of 150 mV/dec, an equivalent oxide thickness of 4.4 +/ - 0.3 nm, and a peak effective mobility of 1100 cm2/Vldrs. For a gate length of 260 nm, the short-channel devices have Vt=+0.5 V and a subthreshold slope of 200 mV/dec. Compared with Schottky-gated high-electron-mobility transistor devices, both long- and short-channel MOSFETs have two to four orders of magnitude lower gate leakage.