Alessio Griffoni

Radiation Effects in Advanced Multiple Gate and Silicon-on-Insulator Transistors

The aim of this review paper is to describe in a comprehensive manner the current understanding of the radiation response of state-of-the-art Silicon-on-Insulator (SOI) and FinFET CMOS technologies. Total Ionizing Dose (TID) response, heavy-ion microdose effects and single-event effects (SEEs) will be discussed. It is shown that a very high TID tolerance can be achieved by narrow-fin SOI FinFET architectures, while bulk FinFETs may exhibit similar TID response to the planar devices. Due to the vertical nature of FinFETs, a specific heavy-ion response can be obtained, whereby the angle of incidence becomes highly important with respect to the vertical sidewall gates. With respect to SEE, the buried oxide in the SOI FinFETs suppresses the diffusion tails from the charge collection in the substrate compared to the planar bulk FinFET devices. Channel lengths and fin widths are now comparable to, or smaller than the dimensions of the region affected by the single ionizing ions or lasers used in testing. This gives rise to a high degree of sensitivity to individual device parameters and source-drain shunting during ion-beam or laser-beam SEE testing. Simulations are used to illuminate the mechanisms observed in radiation testing and the progress and needs for the numerical modeling/simulation of the radiation response of advanced SOI and FinFET transistors are highlighted.

Laser- and Heavy Ion-Induced Charge Collection in Bulk FinFETs

Through-wafer two-photon absorption laser experiments were performed on bulk FinFETs. Transients show distinct signatures for charge collection from drift and diffusion, demonstrating the contribution of charge generated in the substrate to the charge collection process. This result was validated through heavy ion testing on more advanced bulk FinFETs with fin widths as narrow as 5 nm. The drain region dominates the charge collection, with as much as 45 fC of charge collected in the drain region.

Neutron-Induced Failure in Silicon IGBTs, Silicon Super-Junction and SiC MOSFETs

50 MeV and 80 MeV neutron-induced failure is investigated for several types of power devices (super-junction, IGBT and SiC) from different vendors. A strong dependence on the device type and orientation is observed.

Proton-Induced Mobility Degradation in FinFETs With Stressor Layers and Strained SOI Substrates

Proton irradiation effects on fin-type field effect transistors (FinFETs) are examined from the viewpoint of their electrical-performance parameter of mobility. They are fabricated with various types of combination of strain/stress techniques to control their mobilities. The base stress level is globally modified by means of nonstrained or strained silicon-on-insulator wafers. Some process splits, additionally, receive a local strain tuning with a contact-etch-stop layer (CESL). Both n- and p-type FinFETs are evaluated. A 60-MeV proton irradiation with a fluence of 1012 p/cm2 leads to mobility changes for wide-fin samples: degradation for n-type and enhancement for p-type. These mobility variations can be explained with a change in the number of charged interface traps at the Si and buried-oxide interface. Narrow-fin devices exhibit mobility changes unnoticeable statistically. A comparison with previous studies indicates an elevated source/drain structure plays a role in this mobility preservation. Although the mobility is kept intact in the narrow-fin samples, a close investigation based on a two channel-component model can reveal noticeable mobility variations at a component level. In this study, observed mobility changes are complex depending on the adopted stress techniques as well as process parameters and cannot be explained by the stress levels simply.

Characterization and Optimization of Sub-32-nm FinFET Devices for ESD Applications

Electrostatic discharge performance of advanced FinFETs shows a delicate sensitivity to device layout and to processing parameters. Both N- and P-type MOS FinFET devices are characterized in bipolar operation mode as a function of layout parameters such as gate length and fin width. The impact of well implants, selective epitaxial growth, and strain is studied.

Off-State Degradation of High-Voltage-Tolerant nLDMOS-SCR ESD Devices

The OFF-state degradation of n-channel laterally diffused metal-oxide-semiconductor (MOS) silicon-controlled-rectifier electrostatic-discharge (ESD) devices for high-voltage applications in standard low-voltage complementary MOS technology is studied. Based on experimental data and technology computer-aided design simulations, impact ionization induced by conduction-band electrons tunneling from an n+ poly-Si gate to an n-well is identified to be the driving force of device degradation. Device optimization is proposed, which improves both OFF-state and ESD reliability.

A Statistical Approach to Microdose Induced Degradation in FinFET Devices

We study the variability of microdose effects induced by heavy-ion strikes on FinFETs. We model the effects through a statistical analysis, which considers the three-dimensional nature of these devices and overlapping ion hits. The analysis carried out in this work is based on a large amount of experimental data and on the reliability distribution functions (Poisson area scaling, LogNormal distribution, Weibull distribution, etc.), commonly used to estimate the time and charge to breakdown for accelerated lifetime tests.

Microdose and Breakdown Effects Induced by Heavy Ions on Sub 32-nm Triple-Gate SOI FETs

We studied the permanent effects of heavy-ion strikes on decananometer triple-gate SOI devices. We highlighted the role of the geometry and the three-dimensional architecture in the response to heavy ions. Heavy-ion strikes in state-of-the-art Triple-Gate FETs may have measurable permanent effects, due to microdose in the buried oxide, breakdown of the gate oxide, or interface state generation in the side oxide/body interface. This last effect is particularly interesting since it is related to the verticality of multigate transistors.

Advanced ESD power clamp design for SOI FinFET CMOS technology

Two novel ESD power clamp design techniques for SOI FinFET CMOS technology are reported. First, a layout improvement technique is discussed for stacked gated diodes, which reduces the required area for a given ESD robustness and at the same time reduces the on-resistance of the clamp. Secondly, circuit design techniques are used to convert a standard RC-triggered active ESD clamp into a bi-directional design, thereby alleviating the need for a separate reverse protection diode. The concepts can be applied for planar SOI as well.

Degradation of static and dynamic behavior of CMOS inverters during constant and pulsed voltage stress

We study the degradation of CMOS inverters under DC and pulsed stress conditions before the occurrence of the gate oxide breakdown. Our results show an overall speed reduction, caused by the transistor drain current drop, and a leftward shift of the inverter voltage transfer characteristics, due to a larger degradation of the PMOSFET as compared to the NMOSFET. We attribute this behavior to the build-up of defects/trapped charge featuring a different kinetics in P- and N-type MOSFETs.