Mirko Scholz

Investigating ESD sensitivity in electrostatic SiGe MEMS

The sensitivity of electrostatically actuated SiGe microelectromechanical systems to electrostatic discharge events has been investigated in this paper. Torsional micromirrors and RF microelectromechanical systems (MEMS) actuators have been used as two case studies to perform this study. On-wafer electrostatic discharge (ESD) measurement methods, such as the human body model (HBM) and machine model (MM), are discussed. The impact of HBM ESD zap tests on the functionality and behavior of MEMS is explained and the ESD failure levels of MEMS have been verified by failure analysis. It is demonstrated that electrostatic MEMS devices have a high sensitivity to ESD and that it is essential to protect them.

Mechanical response of electrostatic actuators under ESD stress

In this work, the mechanical response of electrostatic MEMS actuators during ESD stress has been measured and reported for the first time. The failure mechanism of the actuators during ESD has been studied and compared with failure under low frequency (∼DC) voltage overstress. Electrical and mechanical failure modes have been distinguished and correlated to enable better understanding of the failure physics. Measuring the mechanical response during ESD stress tests has been demonstrated to be very important to characterize the reliability of electrostatic MEMS actuators. An experimental set-up for the same has been demonstrated and compared with a conventional ESD tester.

ESD protection diodes in optical interposer technology

The ESD robustness of planar Si and Ge diodes on Silicon-on-Insulator (SOI) optical interposer is studied by using TLP and vfTLP system. Although Ge diodes show a lower failure current, a superior clamping capability with a resistance lowering behavior, which is attributed to the intrinsic material properties of Ge, makes Ge diodes possess a promising potential for ESD protections.

Impact of local interconnects on ESD design

Local interconnect (LI) as a contact scheme impacts significant the behavior of protection devices under Electro Static Discharge (ESD) stress. The narrow LI reduces the ESD robustness. At the same time, the on-resistance increases. This makes ESD protection design in future technology nodes more challenging, as the ESD design windows continuously shrinks.

Tunable ESD clamp for high-voltage power I/O pins of a battery charge circuit in mobile applications

A tunable PNP-based ESD clamp is designed for a 4.5V power IO in a foundry technology. Using Mixed-Mode TCAD simulations, we show that the clamps trigger and holding voltage can be easily tuned by simple layout modifications. The fabricated clamp was characterized using an on-wafer TLP system, confirming the tunable Vt1=13.4−16.8V, with Vhold slightly above 10V and It2>1.2A. Finally, the clamp is combined with an off-chip transient voltage suppressors (TVS) to withstand surge stress on system-level.

IC and System ESD Co-design

The trend towards high level integration of the system functional blocks on-chip is eliminating the barrier between the components and systems. System-on-chip (SoC) and system-in-package (SiP) designs now often combine a variety of analog and digital circuit blocks that can directly interface with system ports and therefore may require system level ESD protection capability.

Latch-up at System-Level Stress

Integration of validated stand-alone ESD clamps on chip for system level requirements is not a simple problem. Application specifics and chip functionality need to be thoroughly taken into account to avoid clamp interaction with internal circuit blocks during both system-level ESD stress and normal operation. In high injection conditions induced by system-level ESD current, parasitic devices capable of supporting the conductivity modulation regime may also turn on.

System Level Test Methods

In the previous chapter the major trend toward SoC and SoP integration with system level pins was emphasized. This trend results in the design paradigm shift toward integration of the system level ESD protection capability on-chip. By providing the second stage ESD current capability the on-chip ESD protection can be both used for the IC-system co-design with the PCB components ( Chap. 5) or provide a complete system level compliant pin protection.

On-Chip System Level ESD Devices and Clamps

Design of mixed-signal analog integrated circuits (ICs) often involves a co-design of the internal functional analog circuit blocks, on-chip ESD solutions and even the process integration in case of power optimized technology. Protection of the pins with system-level specification requires an in-depth understanding of a number of rather cross-disciplinary subjects.

System Level ESD Design

An ESD event represents the transfer of energy between two connected objects with different electrostatic potentials until the potentials become equal or the connection is removed. The “connection” assumes the current path provided by any media including air. An ESD event results in a decaying current pulse proportional to the level of the electrostatic potential difference and the rise time and current level determined by the impedance of the connection.