Steven Thijs

A low-power 57-to-66GHz transceiver in 40nm LP CMOS with −17dB EVM at 7Gb/s

Obtaining sufficient EVM in all four 1.76GHz bandwidth chann1.76GHzels specified by IEEE 802.15.3c and the emerging 802.11ad high-data-rate wireless communication standards for modulations as complex as QAM16 is a challenge. Recently reported implementations are therefore restricted to just 1 or 2 channels. Wireless applications often use digital low-power (LP) CMOS technology to implement single-chip transceivers. The high Vt and the thin metal interconnect layers constrain the mm-Wave circuit performance. This paper presents a digital LP 40nm CMOS 60GHz transceiver (TRX) IC that obtains an EVM better than -17dB in all 4 channels.

Mechanical response of electrostatic actuators under ESD stress

In this work, the mechanical response of electrostatic MEMS actuators during ESD stress has been measured and reported for the first time. The failure mechanism of the actuators during ESD has been studied and compared with failure under low frequency (∼DC) voltage overstress. Electrical and mechanical failure modes have been distinguished and correlated to enable better understanding of the failure physics. Measuring the mechanical response during ESD stress tests has been demonstrated to be very important to characterize the reliability of electrostatic MEMS actuators. An experimental set-up for the same has been demonstrated and compared with a conventional ESD tester.

Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies

CMOS scaling beyond 45nm requires devices that deviate from the planar bulk transistor with a polysilicon gate and nitrided silicon dioxide (SiON) as gate dielectric. To downscale planar bulk devices, strain is used to boost mobility and new materials are introduced in the gate stack. Multigate devices such as fully-depleted SOI FinFETs (Fig. 29.4.1) are also candidates for downscaling beyond 45nm.

ESD protection in finfet technologies

▸ Strong dependency on - process technology (SOIFF, bulkFF) - process options (strain, SEG,…) - layout parameters (L<inf>G</inf>, W<inf>fin</inf>,…) ▸ ESD needs to be considered early during technology development ▸ ESD remains very challenging but ▸ ESD is no roadblock for the introduction of both SOIFF and bulkFF!