Alex Barr

Fully-depleted SOI devices with TaSiN gate, HfO 2 gate dielectric, and elevated source/drain extensions

We report for the first time the performance of ultrathin film fully-depleted (FD) silicon-on-insulator (SOI) CMOS transistors using HfO/sub 2/ gate dielectric and TaSiN gate material. The transistors feature 100-150 /spl Aring/ silicon film thickness and selective epitaxial silicon growth in the source/drain extension regions. TaSiN-gate shows good threshold voltage control using an undoped channel, which reduces threshold voltage variation with silicon film thickness and discrete, random dopant placement. Device processing for CMOS fabrication is drastically simplified by the use of the same gate material for both n- and p-MOSFETs. Electrical characterization results illustrate the combined impact of using high-k dielectric and metal gate on the performance of ultrathin film FD SOI devices.

50-nm fully depleted SOI CMOS technology with HfO/sub 2/ gate dielectric and TiN gate

In this paper, we demonstrate for the first time CMOS thin-film metal gate FDSOI devices using HfO/sub 2/ gate dielectric at the 50-nm physical gate length. Symmetric V/sub T/ is achieved for long-channel nMOS and pMOS devices using midgap TiN single metal gate with undoped channel and high-k dielectric. The devices show excellent performance with a I/sub on/=500 /spl mu/A//spl mu/m and I/sub off/=10 nA//spl mu/m at V/sub DD/=1.2 V for nMOSFET and I/sub on/=212 /spl mu/A//spl mu/m and I/sub off/=44 pA//spl mu/m at V/sub DD/=-1.2 V for pMOSFET, with a CET=30 /spl Aring/ and a gate length of 50 nm. DIBL and SS values as low as 70 mV/V nand 77 mV/dec, respectively, are obtained with a silicon film thickness of 14 nm. Ring oscillators with 15 ps stage delay at V/sub DD/=1.2 V are also realized.

Two-dimensional ultrashallow junction characterization of metal-oxide-semiconductor field effect transistors with strained silicon

Strained Si has been realized as one of the most promising candidates of next generation complementary metal-oxide-semiconductor technology. Since the carrier mobility can be significantly increased with strained Si lattice, the device speed can be further increased without reducing the critical dimensions. However, ultrashallow junction engineering becomes more challenging due to much complicated dopant diffusion behavior. We have used scanning capacitance microscopy and dopant selective etching to characterize such differences by comparing the devices fabricated with strained Si channel and with conventional unstrained Si. The devices we used are p-type channel complementary metal-oxide-semiconductor field effect transistors fabricated with 130 nm technology, with strained Si channel built on SiGe pseudosubstrate. Significant differences were observed in the formation of source/drain (S/D) extensions. The junction profile shows abrupt transition from S/D extension to S/D comparing with unstrained Si. Me...

Performance and reliability of sub-100nm TaSiN metal gate fully-depleted SOI devices with high-k (HfO/sub 2/) gate dielectric

In this paper, we report the performance and reliability of sub-100nm TaSiN metal gate fully depleted SOI devices with high-k gate dielectric. Performance differences between fully-depleted and partially-depleted devices are highlighted. This is also the first time that an unique asymmetric degradation phenomenon between electron and hole mobility in metal/high-k devices is reported. Despite the use of high-k dielectric, we show that these devices exhibit superior reliability, noise and analog circuit performances.

Characterization Techniques for Evaluating Strained Si CMOS Materials

The electron and hole mobility of Si complementary metal on oxide field effect transistors (CMOS) can be enhanced by introducing a biaxial tensile stress in the Si channel. This paper outlines several key analytical techniques needed to investigate such layers. Raman scattering is used to measure the strain in the Si channel as well as to map the spatial distribution of strain in Si at a lateral resolution better than 0.5 μm. Atomic force microscopy (AFM) is used to measure the surface roughness. Transmission electron microscopy (TEM) is used to reveal dislocations in the structure, the nature of the dislocations and the propagation of the dislocations. Secondary ion mass spectrometry (SIMS) is used to monitor the Ge content profile in the structure and the thickness of each layer. In the long term, inline nondestructive techniques are desired for epi‐monitoring in manufacturing. Two techniques, spectroscopic ellipsometry (SE) and x‐ray reflectivity (XRR), have shown promise at this stage.

Secondary ion mass spectrometry characterization of source/drain junctions for strained silicon channel metal–oxide–semiconductor field-effect transistors

As complementary metal–oxide–semiconductor (CMOS) devices approach the sub-100-nm dimensions in accordance with Moore’s Law, several major technical barriers exist with the formation of ultrashallow junctions. Strained silicon CMOS devices have the advantages of higher carrier mobility and high current drive. The use of silicon germanium substrates for strain in the silicon channel presents many challenges for CMOS integration including maintaining the channel strain and effect on shallow source/drain (SD) junctions. Low energy secondary ion mass spectrometry (SIMS) has been used to study boron and arsenic diffusion behavior in strained silicon and in SiGe. In addition, diffusion of germanium from the relaxed SiGe into the strained silicon layer will be discussed in relationship with SD implant and annealing. SIMS experimental results will also be compared to theoretical simulation results.

Computer aided design of sub-100 nm strained-Si/Si/sub 1-x/Ge/sub x/ NMOSFET through integrated process and device simulations

Integrated process and device simulations were performed to design sub-100 nm strained-Si/Si/sub 75/Ge/sub 25/ devices. The process and device models were carefully calibrated according to various physical and electrical device characterizations. It is observed that the dopant behavior is highly sensitive to the presence of the SSi/SiGe heterointerface, especially when the SSi thickness is reduced below 10 nm. This points to SSi thickness as a new source of process variation and careful control of the SSi layer is important to maintain consistent device performance. In addition, the Type-II energy-band alignment at the heterointerface also contributes strongly to the short-channel device behavior. This work illustrates the need for accurate heterostructure-based process and device models in order to simulate and design aggressively-scaled strained-Si devices.

Characterization techniques for high-mobility strained Si CMOS

This paper discusses critical characterization techniques for strained Si technology, especially to determine the strain state, thickness, and Ge content in the underlying Si/sub 1-x/Ge/sub x/ alloy pseudosubstrate.