Ted R. White

Performance and Variability Comparisons between Multi-Gate FETs and Planar SOI Transistors

This paper compares the performance and inter-die variability of doped and undoped channel multiple-gate FETs (MUGFETs) with respect to planar SOI devices. We show that doped-channel FinFETs have equivalent variability to narrow-width planar devices. As such, transitions to FinFETs for narrow-width devices will likely incur minimal variability impact. To match the low variability of wide-width planar devices, conversions to undoped channel FinFETs is necessary. Furthermore, good short-channel control has to be maintained since undoped channel devices exhibit increase sensitivity to Tbody relative to doped channel FinFETs due to enhanced fully-depleted channel electrostatics

Mixed-signal performance of sub-100nm fully-depleted SOI devices with metal gate, high K (HfO/sub 2/) dielectric and elevated source/drain extensions

We report for the first time, the digital and analog performance of sub-100nm Fully-Depleted Silicon-On-Insulator (SOI) n and p-MOSFETs using TaSiN gate and HfO/sub 2/ dielectric with elevated Source/Drain (SD) extensions. As CMOS technology continues to scale down, the FDSOI technology offers a potential solution to control short channel effects by reducing the silicon film thickness and a concurrent scaling of the buried oxide thickness. The use of metal gate and thin undoped body offer the additional advantages of 1) suppression of polysilicon depletion effects, 2) elimination of boron penetration, 3) minimizing S/D junction capacitance (Cj), and 4) enhancing transistor matching performance for mixed signal application. High k dielectric is necessary to reduce gate leakage for EOT below 15 to 20/spl Aring/. The intrinsic low-leakage nature of the FDSOI device and its immunity to floating body effect provides much opportunity for ultra-low power digital and analog applications. Physical and electrical analyses of the devices are presented to provide an assessment of the metal gates on high K gate dielectric in combination with fully-depleted device operation in the context of digital and analog circuits.

Uniaxial-biaxial stress hybridization for super-critical strained-si directly on insulator (SC-SSOI) PMOS with different channel orientations.

This paper describes the novel stress engineering of SC-SSOI devices through the interactions between biaxial lattice strain, uniaxial relaxation, process-induced stressor and channel orientation. We have demonstrated a method of uniaxial stress relaxation with compressive capping layer (cESL) to achieve the desired stress configurations for enhanced short-channel SC-SSOIpMOS devices

Strain-Enhanced CMOS Through Novel Process-Substrate Stress Hybridization of Super-Critically Thick Strained Silicon Directly on Insulator (SC-SSOI)

This paper describes a biaxial-uniaxial hybridized strained CMOS technology achieved through selective uniaxial relaxation of thick SSOI, dual-stress nitride capping layer, and embedded SiGe source/drain. Through novel strain engineering, nFET/pFET Idsat enhancements as high as 27%/36% have been achieved for sub-40nm devices at 1V with 30% reduction in gate leakage current, while introducing minimum process complexity. This work demonstrates the scalability of SC-SSOI and its advantages over pure biaxial and single uniaxial strained Si technologies

Metrology Challenges for 45-nm Strained-Si Device Technology

The semiconductor industry has maintained its historical exponential improvement in performance by aggressively scaling transistor dimensions. However, as devices approach sub-100-nm dimensions, scaling becomes more challenging and new materials are required to overcome the fundamental physical limitations imposed by existing materials. For example, as power supply voltages continue to decrease with successive scaling, enhancing carrier mobility using biaxially tensile-stressed Si on relaxed SiGe on SOI and on bulk substrates has become a viable option to sustain continual drive current increase without traditional scaling. Although the addition of strained-Si to conventional MOSFET devices is compatible with existing mainstream CMOS process technology, there are new device and process integration challenges, wafer quality monitoring demands, and stringent requirements for film morphology and strain uniformity, imposing new demands on material characterization. Material requirements for strained-Si CMOS devices include having uniform SiGe thickness, Ge composition, and strain distribution. These are required to maintain uniform device performance as well as low defect density for high minority carrier lifetimes and transconductance, as well as low surface roughness to minimize the impact of interface scattering on carrier mobilities. The parameters of interest in strained-Si CMOS technology include SiGe and Si channel thickness, Ge composition, strain, dislocation density, interface quality, and roughness. Nondestructive inline metrology techniques include spectroscopic ellipsometry for film thickness and Ge composition, X-ray reflectivity for thickness, density, and roughness measurements, X-ray fluorescence for Ge composition, UV-Raman spectroscopy for channel strain characterization, IR photoluminescence for defect detection, and X-ray diffraction for both Ge content and strain measurement. While most of these techniques are well established in the semiconductor industry, some will require development for application to volume manufacturing. This paper will focus on various metrology approaches used in strained-Si CMOS devices

Embedded Source/Drain SiGe Stressor Devices on SOI: Integrations, Performance, and Analyses

A detailed investigation of embedded source/drain SiGe stressors (eSiGes) on a silicon-on-insulator substrate for pMOS performance enhancement is presented. It is found that the integration with undoped SiGe epitaxy suffers strain relaxation from a postepitaxy implantation. SiGe growth with in situ doping is able to retain high strain for carrier mobility enhancement. For doped eSiGe integration with a proper thermal sequence, 20% pMOS drive current improvement is demonstrated. Quantitative analyses of contributions from mobility enhancement and device exterior resistance reduction to the performance improvement are also discussed

Metrology Challenges for 45 nm Strained‐Si Devices

The semiconductor industry has sustained its historical exponential performance gains by aggressively scaling transistor dimensions. However, as devices approach sub‐100 nm dimensions, scaling becomes more challenging and new materials are required to overcome the fundamental physical limits imposed by existing materials. For example, as power supply voltages continue to decrease with successive scaling, enhanced carrier mobility using biaxially tensile‐strained‐Si on SOI or on bulk substrates have become viable options to sustain continual drive current increases without traditional scaling. Although the addition of strained‐Si to conventional MOSFET devices is compatible with existing mainstream CMOS process technology, there are new device and process integration challenges, wafer quality monitoring demands, and stringent requirements for film morphology and strain uniformity, imposing new demands on material characterization. Material requirements for strained‐Si CMOS devices include homogeneous Si or...

Dual Silicide SOI CMOS Integration with Low-Resistance PtSi PMOS Contacts

We demonstrate a dual silicide integration on a SOI CMOS platform with robust low-resistance PtSi PMOS contacts. Compared to NiSi, the specific contact resistivity is reduced in PtSi contacts to p-type Si and increased in contacts to n-type Si. PMOS linear and saturation drive current enhancements of 6% and 9%, respectively, were achieved with PtSi relative to baseline NiSi source/drain contacts.

Uniaxial and Biaxial Strain for CMOS Performance Enhancement

Uniaxial stressors have been mainly employed for boosting PMOS performance, while it is more difficult to increase NMOS performance using tensile stressors. This results in changing the n:p ratio, which requires circuit layout changes. Enhancing both NMOS and PMOS performance to retain the same n:p ratio is desirable. Interactions between biaxial lattice strain, uniaxial relaxation, process-induced stressor and channel orientation have been optimized to achieve the desired stress configurations for enhancing both short-channel SSOI NMOS and PMOS devices

Integration challenges of new materials and device architectures for IC applications

In this paper, we will detail the issues with new materials being introduced into CMOS devices and present some potential solutions to enable high performance and low power CMOS for the 65nm node and beyond.