Alex Hubbard

Three-dimensional wafer stacking using Cu TSV integrated with 45nm high performance SOI-CMOS embedded DRAM technology

For high-volume production of 3D-stacked chips with through-silicon-via (TSVs), wafer-scale bonding offers lower production cost compared with bump bond technology [1][2][3] and is promising for interconnect pitch <;= 5μ range using available tooling. Prior work [3] has presented wafer-scale integration with tungsten TSV for low-power applications. This paper reports the first use of low-temperature oxide bonding and copper TSV to stack high performance cache cores manufactured in 45nm SOI-CMOS embedded DRAM (EDRAM) having 12 to 13 copper wiring levels per strata. A key feature of this process is its compatibility with the existing high performance POWER7™ EDRAM core [4] requiring neither re-design nor modification of the existing CMOS fabrication process. Hardware measurements show no significant impact on device drive and off-current. Functional test at wafer level confirms 1.48GHz 3D stacked EDRAM operation.

Prototype of multi-stacked memory wafers using low-temperature oxide bonding and ultra-fine-dimension copper through-silicon via interconnects

Reported for the first time is proof-of-concept multi-stacking of memory wafers based on low-temperature oxide wafer bonding using novel design and integration of two types of ultra-fine-dimension copper TSV interconnects. The combined via-middle (intra-via) and via-last (inter-via) strategy allows for the greatest degree of interconnectivity with the tightest allowable pitches and permits a highly integrated interconnect system across the stack. In combination with the successful metallization of the ultra-fine-dimension TSVs, the present work has shown the viability to extend the perceived TSV technology beyond the ITRS roadmap.

Wafer-scale oxide fusion bonding and wafer thinning development for 3D systems integration: Oxide fusion wafer bonding and wafer thinning development for TSV-last integration

300mm Si wafer-scale oxide fusion bonding and mechanical/wet etch assisted wafer thinning processes were combined with a TSV-last 3D integration strategy to fabricate electrical open/short yield learning on through-wafer electrical TSV test chains.

Essential edge protection techniques for successful multi-wafer stacking

3D edge protection for wafer scale stacking using oxide bonding has been demonstrated with readily available CMOS compatible processes. Edge voiding has been shown to vastly reduce as well CMP edge removal. By utilizing edge protection schemes such as this, in combination with other approaches for bevel/edge protection for wafer thinning [4], wafer edges can be preserved with minimal additional processing complexity to enable multi-wafer 3D stacking and technologies such as Backside Illuminated Image Sensors (BSI) [9] and 3Dm, all of which can benefit from such an approach.

Driving down defect density in composite EUV patterning film stacks

Extreme ultraviolet lithography (EUVL) technology is one of the leading candidates for enabling the next generation devices, for 7nm node and beyond. As the technology matures, further improvement is required in the area of blanket film defectivity, pattern defectivity, CD uniformity, and LWR/LER. As EUV pitch scaling approaches sub 20 nm, new techniques and methods must be developed to reduce the overall defectivity, mitigate pattern collapse and eliminate film related defect. IBM Corporation and Tokyo Electron Limited (TELTM) are continuously collaborating to develop manufacturing quality processes for EUVL. In this paper, we review key defectivity learning required to enable 7nm node and beyond technology. We will describe ongoing progress in addressing these challenges through track-based processes (coating, developer, baking), highlighting the limitations of common defect detection strategies and outlining methodologies necessary for accurate characterization and mitigation of blanket defectivity in EUV patterning stacks. We will further discuss defects related to pattern collapse and thinning of underlayer films.

Track process monitoring via laser scattering imaging

The growing complexity of photolithography processes necessitates stringent defect monitoring to meet the increasingly rigorous yield requirements. Mitigation of defectivity at the track level involves both product wafer scans, as well as blanket wafer inspections for process monitoring and tool qualification. Some of the common defect types that are characteristic of the track process are comets, striations, water marks, chuck marks, edge effect etc [1]. In this work, we review two case studies that highlight the benefit of using laser-based scattering imaging for detecting coating-induced defects in blanket wafers [2]. First, we used a whole wafer, laser-based scattering image to detect, as well as quantify, a buildup of material near the wafer center. Grid analysis of the whole wafer image enabled us to bin out the defective regions of the wafer surface, and as a result automatically flag defective monitor wafers. Achievement of process improvement is reflected in the post-change process scan images. This methodology of process signature monitoring led to the optimization of the spin coating process which was implemented by the track team. In the second case, whole wafer laser scattering imaging was again successfully used to visually capture the spin coating classical striation signature in a film from a trilayer stack. This was further quantified by using a spectroscopic ellipsometer, which clearly highlighted the thickness variation of the resist film as a function of radius across the wafer with maximum thickness variation was observed near the center of the wafer surface. Further studies for this layer will focus on a quantification strategy for verification of process anomaly. This work was performed by IBM Research and Development at various facilities.