Deepika Priyadarshini

Progress in the development and understanding of advanced low k and ultralow k dielectrics for very large-scale integrated interconnects—State of the art

The improved performance of the semiconductor microprocessors was achieved for several decades by continuous scaling of the device dimensions while using the same materials for all device generations. At the 0.25 μm technology node, the interconnect of the integrated circuit (IC) became the bottleneck to the improvement of IC performance. One solution was introduction of new materials to reduce the interconnect resistance-capacitance. After the replacement of Al with Cu in 1997, the inter- and intralevel dielectric insulator of the interconnect (ILD), SiO2, was replaced about 7 years later with the low dielectric constant (low-k) SiCOH at the 90 nm node. The subsequent scaling of the devices required the development of ultralow-k porous pSiCOH to maintain the capacitance of the interconnect as low as possible. The composition and porosity of pSiCOH dielectrics affected, among others, the resistance of the dielectrics to damage during integration processing and reduced their mechanical strength, thereby af...

Three-dimensional wafer stacking using Cu TSV integrated with 45nm high performance SOI-CMOS embedded DRAM technology

For high-volume production of 3D-stacked chips with through-silicon-via (TSVs), wafer-scale bonding offers lower production cost compared with bump bond technology [1][2][3] and is promising for interconnect pitch <;= 5μ range using available tooling. Prior work [3] has presented wafer-scale integration with tungsten TSV for low-power applications. This paper reports the first use of low-temperature oxide bonding and copper TSV to stack high performance cache cores manufactured in 45nm SOI-CMOS embedded DRAM (EDRAM) having 12 to 13 copper wiring levels per strata. A key feature of this process is its compatibility with the existing high performance POWER7™ EDRAM core [4] requiring neither re-design nor modification of the existing CMOS fabrication process. Hardware measurements show no significant impact on device drive and off-current. Functional test at wafer level confirms 1.48GHz 3D stacked EDRAM operation.

Tungsten and cobalt metallization: A material study for MOL local interconnects

Middle-of-the-line (MOL) interconnect and contact resistances represent significant impacts to high-end IC performance at ≤ 10 nm nodes. CVD W-based metallization has been used for all nodes since the inception of damascene. However, it is now being severely challenged due to limited scaling of the traditional PVD Ti/CVD TiN barrier and ALD nucleation layers. This study reports the use of alternate barriers, along with metal-to-metal contact interface cleans, to reduce contact resistance for W-based MOL metallization. As well, we report the first use of Co metal for MOL contacts and local interconnects, with successful integration below a Cu BEOL dual damascene V0/M1 module. Metal line resistances are compared among the various options, and the challenges with each option are highlighted.

Prototype of multi-stacked memory wafers using low-temperature oxide bonding and ultra-fine-dimension copper through-silicon via interconnects

Reported for the first time is proof-of-concept multi-stacking of memory wafers based on low-temperature oxide wafer bonding using novel design and integration of two types of ultra-fine-dimension copper TSV interconnects. The combined via-middle (intra-via) and via-last (inter-via) strategy allows for the greatest degree of interconnectivity with the tightest allowable pitches and permits a highly integrated interconnect system across the stack. In combination with the successful metallization of the ultra-fine-dimension TSVs, the present work has shown the viability to extend the perceived TSV technology beyond the ITRS roadmap.

BEOL process integration for the 7 nm technology node

A 36 nm pitch BEOL has been evaluated for the 7 nm technology node. EUV lithography was employed as a single-exposure patterning solution. For the first time, it is shown that excellent reliability results can be obtained for Cu interconnects at these small dimensions, by using a TaN/Ru barrier system and a selective Co cap.

Advanced metal and dielectric barrier cap films for Cu low k interconnects

Multi-layer SiN barrier film with high breakdown and low leakage is developed for Cu low k interconnects and is compared with the SiCNH barrier film used at previous technology nodes. Ultra-thin SiN barrier cap film also provides high conformality and fills recess in Cu lines observed post CMP. A significant enhancement in electro migration (EM) performance was obtained by selectively depositing Co on top of Cu lines followed by conformal multi-layer SiN barrier film. Further EM lifetime improvement is obtained by using a Co liner to form a wrap around structure with completely encapsulated Cu. An integrated in-situ preclean/ metal/dielectric cap chamber was used to avoid any oxidation of Cu/Co layers. Kinetic studies of CVD Co liner/Co cap samples show significant increase in EM activation energy (1.7 eV) over samples with dielectric only barrier film (0.9-1 eV). The complete wrap around structure with Co liner and Co cap shows improved device reliability.

Wafer-scale oxide fusion bonding and wafer thinning development for 3D systems integration: Oxide fusion wafer bonding and wafer thinning development for TSV-last integration

300mm Si wafer-scale oxide fusion bonding and mechanical/wet etch assisted wafer thinning processes were combined with a TSV-last 3D integration strategy to fabricate electrical open/short yield learning on through-wafer electrical TSV test chains.

Advanced single precursor based pSiCOH k = 2.4 for ULSI interconnects

A single precursor, octamethylcyclotetrasiloxane (OMCTS), was used to develop a pSiCOH interconnect dielectric with an ultralow dielectric constant k = 2.4. With no added porogen, the advanced pSiCOH dielectric has low pore size and low pore interconnectivity. The new OEx2.4 dielectric has a high carbon content with a significant fraction in the form of Si-CH2-Si bridging bond resulting in a film with relatively high modulus and increased resistance to process induced damage. The new OEx2.4 film shows significant improvement in device reliability (time dependent dielectric breakdown) over the reference k 2.55 and other k 2.4 dielectrics. This dielectric not only addresses the integration challenges but also provides capacitance benefit by retaining an overall lower integrated k value over the reference films. The results discussed in this paper indicate that the single-precursor OMCTS-based advanced pSiCOH, OEX2.4 dielectric is a strong candidate for sub-10 nm Cu/low k interconnects.

Through-Cobalt Self Forming Barrier (tCoSFB) for Cu/ULK BEOL: A novel concept for advanced technology nodes

Through-Co self-forming-barrier (tCoSFB) metallization scheme is introduced, with Cu gap-fill capability down to 7 nm-node dimensions. Mn atoms from doped-seedlayer diffuse through CVD-Co wetting layer, to form TaMnxOy barrier, with integrity proven by vertical-trench triangular-voltage-sweep and barrier-oxidation tests. tCoSFB scheme enables 32% and 45% lower line and via resistance, respectively at 10 nm node dimensions, while achieving superior EM performance to competitive TaN/Co and TaN/Ru-based barriers.

Optimizing ULK film properties to enable BEOL integration with TDDB reliability

Increasing circuit density in multilevel back-end-of line (BEOL) interconnects is necessary to improve integrated circuit performance and area scaling. Ultra low-k (ULK) dielectrics are used to minimize capacitance for lower power consumption and better capacitance-resistance (RC) performance. However, these materials pose integration and reliability challenges, which have limited our ability to scale the dielectric constant lower.1 Minimizing porosity, maximizing carbon content, and altering how carbon is bonded in porous SiCOH films reduces plasma-induced damage (PID) to the ULK and improves TDDB reliability, but these improvement must be balanced by maintaining other film properties such as elastic modulus. This paper describes one technique to achieve this combination of high carbon content and low porosity to allow k scaling while meeting integration and reliability requirements.