Kevin R. Winstel

3D copper TSV integration, testing and reliability

Node-agnostic Cu TSVs integrated with high-K/metal gate and embedded DRAM were used in functional 3D modules. Thermal cycling and stress results show no degradation of TSV or BEOL structures, and device and functional data indicate that there is no significant impact from TSV processing and/or proximity.

Integration of trench DRAM into a high-performance 0.18 /spl mu/m logic technology with copper BEOL

In this work, we demonstrate the integration of trench DRAM into a 0.18 /spl mu/m copper BEOL technology which is fully compatible with our most advanced logic technology and requires no redesign of preexisting logic circuitry. This technology offers a 0.617 /spl mu/m/sup 2/ DRAM cell on the same chip as a 4.2 /spl mu/m/sup 2/ SRAM cell and dual damascene copper metallization with the highest reported device performance for a 1.5 V bulk silicon technology. We demonstrate a fixable retention time of over 256 ms at 85/spl deg/C for the DRAM cell without any degradation in logic device performance or density.

Three-dimensional wafer stacking using Cu TSV integrated with 45nm high performance SOI-CMOS embedded DRAM technology

For high-volume production of 3D-stacked chips with through-silicon-via (TSVs), wafer-scale bonding offers lower production cost compared with bump bond technology [1][2][3] and is promising for interconnect pitch <;= 5μ range using available tooling. Prior work [3] has presented wafer-scale integration with tungsten TSV for low-power applications. This paper reports the first use of low-temperature oxide bonding and copper TSV to stack high performance cache cores manufactured in 45nm SOI-CMOS embedded DRAM (EDRAM) having 12 to 13 copper wiring levels per strata. A key feature of this process is its compatibility with the existing high performance POWER7™ EDRAM core [4] requiring neither re-design nor modification of the existing CMOS fabrication process. Hardware measurements show no significant impact on device drive and off-current. Functional test at wafer level confirms 1.48GHz 3D stacked EDRAM operation.

Low temperature direct wafer to wafer bonding for 3D integration: Direct bonding, surface preparation, wafer-to-wafer alignment

In this paper the integration challenges related to oxide-oxide bonding for wafer-to-wafer stacking technology are discussed. Furthermore, interface defectivity, wafer-to-wafer alignment and bond strength data are presented.

Bonding technologies for chip level and wafer level 3D integration

This paper provides a comparison of bonding process technologies for chip and wafer level 3D integration (3Di). We discuss bonding methods and comparison of the reflow furnace, thermo-compression, Cavity ALignment Method (CALM) for chip level bonding, and oxide bonding for 300 mm wafer level 3Di. For chip 3Di, challenges related to maintaining thin die and laminate co-planarity were overcome. Stacking of large thin Si die with 22 nm CMOS devices was achieved. The size of the die was more than 600 mm2. Also, 300 mm 3Di wafer stacking with 45 nm CMOS devices was demonstrated. Wafers thinned to 10 μm with Cu through-silicon-via (TSV) interconnections were formed after bonding to another device wafer. In either chip or wafer level 3Di, testing results show no loss of integrity due to the bonding technologies.

Prototype of multi-stacked memory wafers using low-temperature oxide bonding and ultra-fine-dimension copper through-silicon via interconnects

Reported for the first time is proof-of-concept multi-stacking of memory wafers based on low-temperature oxide wafer bonding using novel design and integration of two types of ultra-fine-dimension copper TSV interconnects. The combined via-middle (intra-via) and via-last (inter-via) strategy allows for the greatest degree of interconnectivity with the tightest allowable pitches and permits a highly integrated interconnect system across the stack. In combination with the successful metallization of the ultra-fine-dimension TSVs, the present work has shown the viability to extend the perceived TSV technology beyond the ITRS roadmap.

Wafer-scale oxide fusion bonding and wafer thinning development for 3D systems integration: Oxide fusion wafer bonding and wafer thinning development for TSV-last integration

300mm Si wafer-scale oxide fusion bonding and mechanical/wet etch assisted wafer thinning processes were combined with a TSV-last 3D integration strategy to fabricate electrical open/short yield learning on through-wafer electrical TSV test chains.

Essential edge protection techniques for successful multi-wafer stacking

3D edge protection for wafer scale stacking using oxide bonding has been demonstrated with readily available CMOS compatible processes. Edge voiding has been shown to vastly reduce as well CMP edge removal. By utilizing edge protection schemes such as this, in combination with other approaches for bevel/edge protection for wafer thinning [4], wafer edges can be preserved with minimal additional processing complexity to enable multi-wafer 3D stacking and technologies such as Backside Illuminated Image Sensors (BSI) [9] and 3Dm, all of which can benefit from such an approach.

Copper-to-dielectric heterogeneous bonding for 3D integration

A novel hybrid bonding process has been developed that achieved a successful copper/SiO2 heterogeneous bonding.