Alexander Edward

General Analysis of Feedback DAC's Clock Jitter in Continuous-Time Sigma-Delta Modulators

This brief describes a framework for the analysis of continuous-time sigma-delta (ΣΔ) modulators (CTSDM) in the presence of a feedback digital-to-analog converter (DAC)s clock jitter using the discrete-time Volterra series. A time-domain mixing operation between jitter and CTSDMs digital output sequence is modeled with a second-order Volterra operator. The resulting closed-form jitter-induced CTSDMs output power spectral density is simple and includes the effects of the following: 1) quantization noise power; 2) input signal power and frequency; 3) CTSDMs quantization noise transfer function; 4) DACs pulse shape; and 5) colored jitter. A third-order CTSDM is analyzed as a test bed. Excellent agreement between theoretical predictions and behavioral simulations is observed.

A 4 Bit Continuous-Time

This paper presents a fully digital quantization noise reduction algorithm (DQNRA) for CTΣΔM. The algorithm overcomes the signal leakage issues commonly found in cascade and MASH implementations. The proposed DQNRA is robust to PVT variations. The DQNRA performs a foreground measurement of the modulators noise transfer function. A ΣΔM using a 7 bit quantizer, from which the four most significant bits are used for the operation of the ΣΔM, proves the DQNRA concept. The remaining three least significant bits are used for the realization of the DQNRA for quantization noise improvement. A 7 bit quantizer with a three-step subranging architecture is implemented to reduce power and area consumption. A fourth-order continuous-time ΣΔ prototype was implemented in 130 nm CMOS technology. The modulators total power consumption is 20 mW, with only 6 mW used for the realization of the 7 bit quantizer operating at 500 MHz. For this prototype, the use of a DQNRA algorithm improved the modulators SNDR from 69 to 75 dB over a 15 MHz bandwidth, limited after calibration by thermal noise rather than quantization noise. The obtained FoM is 164 dB.

\Sigma \Delta

A wide bandwidth, power efficient continuous-time ΣΔ modulator (CTΣΔM) is presented. The modulator introduces a 3rd order filter implemented with a lossless integrator and a multiple-feedback (MFB) single-amplifier biquad (SAB) with embedded loop stability compensation. An active summing block is implemented with a common-gate amplifier followed by a transimpedance amplifier (TIA) that achieves optimum bandwidth (BW) vs power consumption tradeoff, making it suitable for over GHz operation. Fabricated in 40 nm CMOS, and clocked at 3.2 GHz, the CTΣΔM achieves a signal-to-noise and distortion ratio (SNDR) of 64.9 dB over 75 MHz BW while consuming 22.8 mW of power. The obtained Waldens Figure of Merit (FoM) is 106 fJ/conv-step.

Modulator With Fully Digital Quantization Noise Reduction Algorithm Employing a 7 Bit Quantizer

This chapter provides a theoretical review on analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). An in-depth study of signal processing operations including sampling, quantization, requantization, and reconstruction of Nyquist data converters follow.

A 75 MHz BW 68dB DR CT-ΣΔ modulator with single amplifier biquad filter and a broadband low-power common-gate summing technique

This chapter provides a general overview on the discrete-time ΔΣMs (DTΣΔΣMs) and continuous-time ΔΣMs (CTΔΣMs). An introduction on two different topologies of implementing high-order CTΔΣMs, single-loop and MASH, is presented. The benefits of employing a MASH topology for CT-ΔΣMs are also discussed in this chapter.

Analog-to-Digital and Digital-to-Analog Converters

This chapter presents the analysis and design of continuous-time ΔΣ modulators (CTΔΣMs) with a focus on single-loop topology. The methodology of mapping the noise transfer function (NTF) from discrete-time to continuous-time is explained with a design example of a fifth-order CTΔΣM. The anti-aliasing characteristics of feedback and feedforward loop filter topologies are compared. The effects of non-idealities such as the excess loop delay (ELD) and the feedback DAC’s clock jitter on the performance of CTΔΣMs are discussed. A 75-MHz single-loop CTΔΣM prototype is presented as a design example. It was fabricated in a low-power 40-nm CMOS technology, employing a broadband low-power highly efficient common-gate summing stage. This knowledge on single-loop CTΔΣMs is fundamental for the analysis and design of MASH CTΔΣMs.

Delta-Sigma Modulators

This chapter presents a fully digital quantization noise reduction algorithm (DQNRA) for a multistage noise-shaping (MASH) 4-0 continuous-time ΔΣ modulator (CTΔΣM). The presented algorithm is robust to process voltage and temperature (PVT) variations and overcomes the quantization noise leakage issues. A CTΔΣM employs a 7-bit quantizer, from which the four most significant bits are used in a fourth-order ΔΣM loop. The remaining three least significant bits are used for the DQNRA to improve the quantization noise cancelation. The presented MASH 4-0 CTΔΣM prototype was implemented in 130 nm CMOS technology. The modulator’s total power consumption is 20 mW and the 7-bit quantizer consumes only 6 mW operating at 500 MHz. For this prototype, the DQNRA algorithm improved the modulator’s signal-to-noise and distortion ratio (SNDR) from 69 to 75 dB within a 15 MHz bandwidth.

Design of Continuous-Time Delta-Sigma Modulators

This chapter presents a MASH 2-2 CTΔΣM with on-chip RC time-constant calibration circuits, multiple feedforward interstage paths, and a fully integrated noise cancelation filter (NCF). The core modulator architecture is a cascade of two single-loop second-order CTΔΣM stages, each of which consists of an integrator-based active-RC loop filter, current-steering feedback digital-to-analog converters, and a four-bit Flash quantizer. On-chip RC time-constant calibration circuits and high-gain multi-stage operational amplifiers are realized to mitigate quantization noise leakage due to process variation. Multiple feedforward interstage paths are introduced to (1) synthesize a fourth-order noise transfer function with DC zeros, (2) simplify the design of NCF, and (3) reduce signal swings at the second-stage integrator outputs. Fully integrated in 40 nm CMOS, the prototype chip achieves 74.4 dB of signal-to-noise and distortion ratio (SNDR), 75.8 dB of signal-to-noise ratio, and 76.8 dB of dynamic range in 50.3 MHz of bandwidth (BW) at 1 GHz of sampling frequency with 43 mW of power (P) from 1.1, 1.15, and 2.5-V power supplies. It does not require external software calibration and possesses minimal out-of-band signal transfer function (STF) peaking.

MASH 4-0 CT ΔΣ M with Fully Digital Quantization Noise Reduction Algorithm

This chapter focuses on the analysis and design of MASH continuous-time ΔΣ modulators (CTΔΣMs). The architecture synthesis process and design considerations of MASH CTΔΣMs are described based on a MASH 2-2 CTΔΣM topology. This chapter also provides a detailed mathematical analysis and simulation results on the effects of major nonidealities, including the thermal noise, DAC clock jitter, DAC mismatch, and process variations.

MASH 2-2 CT ΔΣ M with Fully Integrated Quantization Noise Leakage Calibration

This chapter discusses the design of a MASH 1-1-1 CTΔΣM employing finite impulse response (FIR) digital-to-analog converters (DACs) and encoder-embedded loop-unrolling (EELU) quantizers. The presented MASH 1-1-1 topology is a cascade of three single-loop first-order CTΔΣM stages. Each stage consists of an active-RC integrator, a current-steering DAC, and an EELU quantizer. An FIR filter in the main 1.5-bit DAC improves the modulator’s jitter sensitivity performance. The FIR’s effect on the noise transfer function (NTF) of the modulator is compensated in the digital domain, thanks to the MASH topology. Instead of employing a conventional analog direct feedback path, a 1.5-bit EELU quantizer based on multiplexing among comparator outputs is presented. Fabricated in a 40-nm low-power CMOS technology, the modulator’s prototype achieves a 67.3 dB of signal-to-noise and distortion ratio (SNDR) within 50.5 MHz of bandwidth (BW), consuming 19.0 mW of total power (P).