Qiyuan Liu

A 43-mW MASH 2-2 CT

This paper proposes a multistage noise-shaping continuous-time sigma-delta modulator (CT<inline-formula> <tex-math notation=LaTeX>

\Sigma \Delta

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Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS

</tex-math></inline-formula>) with on-chip <italic>RC</italic> time constant calibration circuits, multiple feedforward interstage paths, and a fully integrated noise-cancellation filter (NCF). The core modulator architecture is a cascade of two single-loop second-order CT<inline-formula> <tex-math notation=LaTeX>

A 35 dBm Output Power and 38 dB Linear Gain PA With 44.9% Peak PAE at 1.9 GHz in 40 nm CMOS

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A Low-Power Digitizer for Back-Illuminated 3-D-Stacked CMOS Image Sensor Readout With Passing Window and Double Auto-Zeroing Techniques

</tex-math></inline-formula> stages, each of which consists of an integrator-based active- <italic>RC</italic> loop filter, current-steering feedback digital-to-analog converters, and a 4-b flash quantizer. On-chip <italic>RC</italic> time constant calibration circuits and high-gain multistage operational amplifiers are realized to mitigate quantization noise leakage due to process variation. Multiple feedforward interstage paths are introduced to: 1) synthesize a fourth-order noise transfer function with dc zeros; 2) simplify the design of NCF; and 3) reduce signal swings at the second-stage integrator outputs. Fully integrated in 40-nm CMOS, the prototype chip achieves 74.4 dB of signal-to-noise-and-distortion ratio (SNDR), 75.8 dB of signal-to-noise ratio, and 76.8 dB of dynamic range in 50.3 MHz of bandwidth (BW) at 1 GHz of sampling frequency with 43 mW of power consumption (P) from 1.1/1.15/2.5-V power supplies. It does not require external software calibration and possesses minimal out-of-band signal transfer function peaking. The figure-of-merit (FOM), defined as <inline-formula> <tex-math notation=LaTeX>

Analog-to-Digital and Digital-to-Analog Converters

text {FOM}=text {SNDR}+10times log _{10}(text {BW}/text {P})

Delta-Sigma Modulators

</tex-math></inline-formula>, is 165.1 dB.

Design of Continuous-Time Delta-Sigma Modulators

This paper presents a 1.9 GHz linear power amplifier (PA) architecture that improves its power efficiency in the power back-off (PBO) region. The combination of power transistor segmentation and digital gain compensation effectively enhances its power efficiency. A fast switching scheme is proposed, such that PA drivers and segments are switched ON and OFF according to signal power; thus, the PA power consumption correlates with the power of the input signal. Binary power gain variations due to PA segmentation are dynamically compensated in the digital domain. The proposed solution overcomes the tradeoffs between power efficiency and linearity by employing the digital predistortion technique. The PA is implemented in a 40 nm CMOS process. It delivers a saturated output power of 35 dBm with 44.9% peak power-added efficiency (PAE) and a linear gain of 38 dB. The adjacent channel leakage ratio (ACLR) at ±5 MHz at a maximum linear output power of 31 dBm for a baseband WCDMA signal is -35.8 dBc.

MASH 4-0 CT ΔΣ M with Fully Digital Quantization Noise Reduction Algorithm

This paper presents a high-performance digitizer based on column-parallel single-slope analog-to-digital converter (SS-ADC) topology for readout of a back-illuminated 3-D-stacked CMOS image sensor. To address the high power consumption issue in high speed digital counters, a passing window (PW)-based hybrid counter topology is proposed. In this approach, the memory cells in the digital counters of SS-ADCs are disconnected from the global bus during non-relevant timing. To address the high column fixed pattern noise (FPN) under bright illumination conditions, a double auto-zeroing (AZ) scheme is proposed. In this technique, the AZ process is employed twice at reset and signal level, respectively. The double AZ scheme not only allows the comparator to serve as a crossing detector around the common-mode level, but it also enables low-voltage comparator design. The proposed techniques are experimentally verified in a prototype chip designed and fabricated in the TSMC 40 nm low-power CMOS process. The PW technique saves 52.8% of power consumption in the hybrid digital counters. Dark/bright column FPN of 0.0024%/0.028% is achieved employing the proposed double AZ technique for digital correlated double sampling. A single-column digitizer consumes a total power of 66.8 <inline-formula> <tex-math notation=LaTeX>

MASH 2-2 CT ΔΣ M with Fully Integrated Quantization Noise Leakage Calibration

mu text{W}