Alexander Reznicek

Recent Progress and Challenges in Enabling Embedded Si:C Technology

Summary In summary, this work demonstrates that integrating ISPD eSi:C stressor in the thick-oxide long-channel nMOS source and drain is feasible. Key challenges lie in both high-quality ISPD eSi:C EPI development and modification of the conventional Si CMOS fabrication process to preserve eSi:C strain. Acknowledgements This work was performed by IBM/AMD/Freescale Alliance Teams at various IBM Research and Development Facilities. We wish to thank Applied Materials and ASM America for supplying high quality eSi:C EPI materials. References: [1] Kah-Wee Ang, King-Jien Chui, Vladimir Bliznetsov, Yihua Wang, Lai-Yin Wong, Chih-Hang Tung, N. Balasubramanian, Ming-Fu Li, Ganesh Samudra, and Yee-Chia Yeo, IEDM Tech. Dig., p503, 2005.[2] Yaocheng Liu, Oleg Gluschenkov, Jinghong Li, Anita Madan, Ahmet Ozcan, Byeong Kim, Tom Dyer, Ashima Chakravarti, Kevin Chan, Christian Lavoie, Irene Popova, Teresa Pinto, Nivo Rovedo, Zhijiong Luo, Rainer Loesing, William Henson, Ken Rim, Symp. on VLSI Tech., p.44, 2007. [3] P. Grudowski, V. Dhandapani, S. Zollner, D. Goedeke, K. Loiko, D. Tekleab, V. Adams, G. Spencer, H. Desjardins, L. Prabhu, R. Garcia, M. Foisy, D. Theodore, M. Bauer, D. Weeks, S. Thomas, A. Thean, B. White, SOI Conf. Proc., p.17, 2007. [4] Zhibin Ren, G. Pei, J. Li, F. Yang, R. Takalkar, K. Chan, G. Xia, Z. Zhu, A. Madan, T. Pinto, T. Adam, J. Miller, A. Dube, L. Black, J. W. Weijtmans, B. Yang, E. Harley, A. Chakravarti, T. Kanarsky, I. Lauer, D.-G. Park, D. Sadana, and G. Shahidi, Symp. on VLSI Tech., P. 172-173, 2008. [5] A. Madan, J. Li, Z. Ren, F. Yang, E. Harley, T. Adam, R. Loesing, Z. Zhu, T. Pinto, A. Chakravarti, A. Dube, R. Takalkar, J. W. Weijtmans, L. Black, D. Schepis, ECS SiGe and Realted Materials and Devices Symposium, Hawaii, Oct. 2008 (to be published).

Mixed Orientation Si–Si Interfaces by Hydrophilic Bonding and High Temperature Oxide Dissolution

In this paper, we describe a quasi-hydrophobic bonding method in which ultrathin (<1-2 nm) oxide, present on wafer surfaces during bonding, is removed after bonding by a high temperature oxide dissolution anneal to leave the desired direct Si-to-Si contact at the bonded interface. We show that the direct-silicon-bonded (DSB) interfaces produced by this method are clean enough to allow implementation of a recently described amorphization/templated recrystallization technique for changing the orientation of selected DSB layer regions from their original orientation to the orientation of the underlying handle wafer. We then present results from a related study on the dissolution of oxide layers disposed between a Si substrate and a polycrystalline overlayer, and discuss mechanisms most likely to be operative for our oxide dissolution observations.

CMOS Scaling Beyond 22 nm Node

Silicon CMOS scaling continues to defy all previous doom and gloom scenarios and is poised to extend to 15 nm node. There is a paradigm shift though; in previous generations of CMOS (before 90 nm) both performance and transistor density scaling could be achieved simultaneously with passive cooling. Currently, the density scaling appears to continue unabated due to advances in optical lithography (immersion, phase contrast imaging, double exposure, etc). However, performance scaling requires power-performance trade off consideration as the peak performance is limited by heat dissipation that can be managed via passive cooling (< 100 watts/cm 2 ). Nevertheless, performance targets for CMOS products are being met at system level by multi-core architecture which allows massive parallel data processing. Current and future CMOS scaling is undoubtedly being driven by innovations at all levels, including system architecture, circuit design, integration, device design and new high mobility channel materials. This presentation is focused on the channel materials which we believe are most promising for future CMOS nodes.

Advanced Applications of Semiconductor Epitaxy for Cutting Edge Integrated Circuit Technolgy

Silicon and silicon germanium epitaxy is playing a pivotal role in current CMOS technology. The application of semiconductor epitaxy in the past was mainly confined to hetero junction bipolar technology (HBT) to control boron doping profile in the base region, and to provide p Si layer for CMOS. However, as CMOS scaling is becoming increasingly difficult, exploitation of strain-Si in the channel region to boost CMOS performance has given epitaxy a new place in IC fabrication. Selective SiGe epitaxial growth in the source-drain and extension regions of a pFET is already in production for 90 and 65 nm CMOS to provide strained Si channel. Ultimate CMOS of the future is envisioned to have non-Si channels including Ge and III-V compounds. Epitaxy, whether CVD based (RPCVD, UHCVD) or MBE, will play a central role for semiconductor material development. In this review we will describe relatively new applications of epitaxy for advanced hybrid oriented technology (HOT) viz SuperHOT, and a single wafers sSOI process by SIMOX.