Alexander Serb

Unsupervised learning in probabilistic neural networks with multi-state metal-oxide memristive synapses

In an increasingly data-rich world the need for developing computing systems that cannot only process, but ideally also interpret big data is becoming continuously more pressing. Brain-inspired concepts have shown great promise towards addressing this need. Here we demonstrate unsupervised learning in a probabilistic neural network that utilizes metal-oxide memristive devices as multi-state synapses. Our approach can be exploited for processing unlabelled data and can adapt to time-varying clusters that underlie incoming data by supporting the capability of reversible unsupervised learning. The potential of this work is showcased through the demonstration of successful learning in the presence of corrupted input data and probabilistic neurons, thus paving the way towards robust big-data processors.

Analog Memristive Synapse in Spiking Networks Implementing Unsupervised Learning

Emerging brain-inspired architectures call for devices that can emulate the functionality of biological synapses in order to implement new efficient computational schemes able to solve ill-posed problems. Various devices and solutions are still under investigation and, in this respect, a challenge is opened to the researchers in the field. Indeed, the optimal candidate is a device able to reproduce the complete functionality of a synapse, i.e., the typical synaptic process underlying learning in biological systems (activity-dependent synaptic plasticity). This implies a device able to change its resistance (synaptic strength, or weight) upon proper electrical stimuli (synaptic activity) and showing several stable resistive states throughout its dynamic range (analog behavior). Moreover, it should be able to perform spike timing dependent plasticity (STDP), an associative homosynaptic plasticity learning rule based on the delay time between the two firing neurons the synapse is connected to. This rule is a fundamental learning protocol in state-of-art networks, because it allows unsupervised learning. Notwithstanding this fact, STDP-based unsupervised learning has been proposed several times mainly for binary synapses rather than multilevel synapses composed of many binary memristors. This paper proposes an HfO2-based analog memristor as a synaptic element which performs STDP within a small spiking neuromorphic network operating unsupervised learning for character recognition. The trained network is able to recognize five characters even in case incomplete or noisy images are displayed and it is robust to a device-to-device variability of up to ±30%.

Implementation of a spike-based perceptron learning rule using TiO2−x memristors

Synaptic plasticity plays a crucial role in allowing neural networks to learn and adapt to various input environments. Neuromorphic systems need to implement plastic synapses to obtain basic “cognitive” capabilities such as learning. One promising and scalable approach for implementing neuromorphic synapses is to use nano-scale memristors as synaptic elements. In this paper we propose a hybrid CMOS-memristor system comprising CMOS neurons interconnected through TiO2−x memristors, and spike-based learning circuits that modulate the conductance of the memristive synapse elements according to a spike-based Perceptron plasticity rule. We highlight a number of advantages for using this spike-based plasticity rule as compared to other forms of spike timing dependent plasticity (STDP) rules. We provide experimental proof-of-concept results with two silicon neurons connected through a memristive synapse that show how the CMOS plasticity circuits can induce stable changes in memristor conductances, giving rise to increased synaptic strength after a potentiation episode and to decreased strength after a depression episode.

A memristor SPICE model accounting for synaptic activity dependence

In this work, we propose a new memristor SPICE model that accounts for the typical synaptic characteristics that have been previously demonstrated with practical memristive devices. We show that this model could account for both volatile and non-volatile memristance changes under distinct stimuli. We then demonstrate that our model is capable of supporting typical STDP with simple non-overlapping digital pulse pairs. Finally, we investigate the capability of our model to simulate the activity dependence dynamics of synaptic modification and present simulated results that are in excellent agreement with biological results.

Practical Determination of Individual Element Resistive States in Selectorless RRAM Arrays

Three distinct methods of reading multi-level cross-point resistive states from selector-less RRAM arrays are implemented in a physical system and compared for read-out accuracy. They are: the standard, direct measurement method and two methods that attempt to enhance accuracy by computing cross-point resistance on the basis of multiple measurements. Results indicate that the standard method performs as well as or better than its competitors. SPICE simulations are then performed with controlled amounts of non-idealities introduced in the system in order to test whether any technique offers particular resilience against typical practical imperfections such as crossbar line resistance. We conclude that even though certain non-idealities are shown to be minimized by different circuit-level read-out strategies, line resistance within the crossbar remains an outstanding challenge.

An FPGA-based instrument for en-masse RRAM characterization with ns pulsing resolution

An FPGA-based instrument with capabilities of on-board oscilloscope and nanoscale pulsing (70 ns @ ±10 V) is presented, thus allowing exploration of the nano-scale switching of RRAM devices. The system possesses less than 1% read-out error for resistance range between 1 kΩ to 1 MΩ, and demonstrated its functionality on characterizing solid-state prototype RRAM devices on wafer; devices exhibiting gradual switching behavior under pulsing with duration spanning between 30 ns to 100 μs. The data conversion error-induced degradation on read-out accuracy is studied extensively and verified by standard linear resistor measurements. The integrated oscilloscope capability extends the versatility of our instrument, rendering a powerful tool for processing development of emerging memory technologies but also for testing theoretical hypotheses arising in the new field of memristors.

Towards a memristor-based spike-sorting platform

We present a new approach for performing spike-sorting through a memristor-based, neural-signal processing platform. We have previously shown that the inherent threshold property of the memristor allows spike-detection through nonvolatile resistive state transition. Here, a test memristive device is subjected to a neural recording and the periodically recorded resistive state changes are mapped to the amplitude of the spiking events. It is found that the resistive state changes can be differentiated into clusters, where each cluster can be mapped to a range of spiking events in the input neural waveform, thus indicating the address of source neuron.

X-Ray spectromicroscopy investigation of soft and hard breakdown in RRAM devices

Resistive random access memory (RRAM) is considered an attractive candidate for next generation memory devices due to its competitive scalability, low-power operation and high switching speed. The technology however, still faces several challenges that overall prohibit its industrial translation, such as low yields, large switching variability and ultimately hard breakdown due to long-term operation or high-voltage biasing. The latter issue is of particular interest, because it ultimately leads to device failure. In this work, we have investigated the physicochemical changes that occur within RRAM devices as a consequence of soft and hard breakdown by combining full-field transmission x-ray microscopy with soft x-ray spectroscopic analysis performed on lamella samples. The high lateral resolution of this technique (down to 25 nm) allows the investigation of localized nanometric areas underneath permanent damage of the metal top electrode. Results show that devices after hard breakdown present discontinuity in the active layer, Pt inclusions and the formation of crystalline phases such as rutile, which indicates that the temperature increased locally up to 1000 K.

A data-driven Verilog-A ReRam model

The translation of emerging application concepts that exploit resistive random access memory (ReRAM) into large-scale practical systems requires realistic yet computationally efficient device models. Here, we present a ReRAM model, where device current–voltage characteristics and resistive switching rate are expressed as a function of: 1) bias voltage and 2) initial resistive state (RS). The model versatility is validated on detailed characterization data, for both filamentary valence change memory and nonfilamentary ReRAM technologies, where device resistance is swept across its operating range using multiple input voltage levels. Furthermore, the proposed model embodies a window function which features a simple mathematical form analytically describing RS response under constant bias voltage as extracted from physical device response data. Its Verilog-A implementation captures the ReRAM memory effect without requiring integration of the model state variable, making it suitable for fast and/or large-scale simulations and overall interoperable with current design tools.

A memristor-CMOS hybrid architecture concept for on-line template matching

The ability to identify (detect) and categorise (sort) neural spikes in real-time and under highly restrictive power/area budgets is a major enabling technology towards the development of intelligent implantable systems. In this work we propose a memristor-CMOS hybrid architecture concept that relies on a ‘template pixel’ (texel) circuit combining CMOS and memristive devices to perform on-line spike sorting through template matching. We show through simulation how the texel is capable of comparing an input voltage against a stored (in the memristors) value and converting the degree of matching between input and stored pattern into a current. We further illustrate the fundamental texel design space that includes tuning it to a different preferred input voltage and controlling the sharpness of the tuning. Finally, we estimate that even in an unoptimised technology and design a texel array capable of recognising three different 10-point patterns will consume a very promising maximum of 3.15 μW for a footprint of approx. 500 μτΉ2.