Alexander Tritchkov

Double pattern EDA solutions for 32nm HP and beyond

The fate of optical-based lithography hinges on the ability to deploy viable resolution enhancement techniques (RET). One such solution is double patterning (DP). Like the double-exposure technique, double patterning is a decomposition of the design to relax the pitch that requires dual masks, but unlike double-exposure techniques, double patterning requires an additional develop and etch step, which eliminates the resolution degradation due to the cross-coupling that occurs in the latent images of multiple exposures. This additional etch step is worth the effort for those looking for an optical extension [1]. The theoretical k1 for a double-patterning technique of a 32nm half-pitch (HP) design for a 1.35NA 193nm imaging system is 0.44 whereas the k1 for a single-exposure technique of this same design would be 0.22 [2], which is sub-resolution. There are other benefits to the DP technique such as the ability to add sub-resolution assist features (SRAF) in the relaxed pitch areas, the reduction of forbidden pitches, and the ability to apply mask biases and OPC without encountering mask constraints. Similarly to AltPSM and SRAF techniques one of the major barriers to widespread deployment of double patterning to random logic circuits is design compliance with split layout synthesis requirements [3]. Successful implementation of DP requires the evolution and adoption of design restrictions by specifically tailored design rules. The deployment of double patterning does spawn a couple of issues that would need addressing before proceeding into a production environment. As with any dual-mask RET application, there are the classical overlay requirements between the two exposure steps and there are the complexities of decomposing the designs to minimize the stitching but to maximize the depth of focus (DoF). In addition, the location of the design stitching would require careful consideration. For example, a stitch in a field region or wider lines is preferred over a transistor region or narrower lines. The EDA industry will be consulted for these sound automated solutions to resolve double-patterning sensitivities and to go beyond this with the coupling of their model-based and process-window applications. This work documented the resolution limitations of single exposure, and double-patterning with the latest hyper-NA immersion tools and with fully optimized source conditions. It demonstrated the best known methods to improve design decomposition in an effort to minimize the impact of mask-to-mask registration and process variance. These EDA solutions were further analyzed and quantified utilizing a verification flow.

Characterization and correction of optical proximity effects in deep‐ultraviolet lithography using behavior modeling

We present the characterization of optical proximity effects and their correction in deep‐UV lithography using an empirically derived model for calculating feature sizes in resist. The model is based on convolution of the mask pattern with a set of kernels determined from measuring the printed test structures in resist. The fit of the model to the measurement data is reviewed. The model is then used for proximity correction using commercially available proximity correction software. Corrections based on this model is effective in restoring resist linearity and in reducing line‐end shortening. It is also more effective in reducing optical proximity effects than corrections based only on aerial image calculations.

Computational lithography: Exhausting the resolution limits of 193-nm projection lithography systems

In the recent past, scaling of semiconductor fabrication systems has been dominated by wavelength and numerical aperture modifications. This is now no longer the case for 193-nm immersion projection lithography (193i) systems as there are no technical paths for continued benefit from the in these areas. Instead, a range of techniques including patterning processes and system optimization are being used to push the limits of the system. This paper will review the elements that are now driving scaling for a system of fixed wavelength and numerical aperture.

Lithography simulation with aerial image - Variable threshold resist model

This paper explores the concept of a variable threshold resist model (VTRM) where the model is trained with data from a specific resist process, and may be applied to lithography simulation for that resist process with a wide variety of optical exposure conditions. This type of simulation is based on aerial image simulation and the application of a simple algebraic formula. It is therefore, very fast and applicable to a wide variety of simulation applications. We have trained the model with the 248nm resists TOK TDUR022 and Shipley UV6. In both cases the model does a good job of capturing most resist dynamics over a wide range of dose, critical dimension (CD), pitch, focus, and partial coherence conditions.

Demonstrating the benefits of source-mask optimization and enabling technologies through experiment and simulations

In recent years the potential of Source-Mask Optimization (SMO) as an enabling technology for 22nm-and-beyond lithography has been explored and documented in the literature.1-5 It has been shown that intensive optimization of the fundamental degrees of freedom in the optical system allows for the creation of non-intuitive solutions in both the mask and the source, which leads to improved lithographic performance. These efforts have driven the need for improved controllability in illumination5-7 and have pushed the required optimization performance of mask design.8, 9 This paper will present recent experimental evidence of the performance advantage gained by intensive optimization, and enabling technologies like pixelated illumination. Controllable pixelated illumination opens up new regimes in control of proximity effects,1, 6, 7 and we will show corresponding examples of improved through-pitch performance in 22nm Resolution Enhancement Technique (RET). Simulation results will back-up the experimental results and detail the ability of SMO to drive exposure-count reduction, as well as a reduction in process variation due to critical factors such as Line Edge Roughness (LER), Mask Error Enhancement Factor (MEEF), and the Electromagnetic Field (EMF) effect. The benefits of running intensive optimization with both source and mask variables jointly has been previously discussed.1-3 This paper will build on these results by demonstrating large-scale jointly-optimized source/mask solutions and their impact on design-rule enumerated designs.

Inverse lithography for 45-nm-node contact holes at 1.35 numerical aperture

Inverse lithography technology (ILT) is a procedure that optimizes the mask layout to produce an image at the wafer with the targeted aerial image. For an illumination condition optimized for dense pitches, ILT inserts model-based subresolution assist features (AF) to improve the imaging of isolated features. ILT is ideal for random contact hole patterns, in which the AF are not at intuitive locations. The raw output of ILT consists of very complex smooth shapes that must be simplified for an acceptable mask write time. It is challenging for ILT to quickly converge to the ideal pattern as well as to simplify the pattern to one that can be manufactured quickly. ILT has many parameters that effect process latitude, background suppression, conversion run time, and mask write time. In this work, an optimization procedure is introduced to find the best tradeoff between image quality and run time or write time. A conversion run time reduction of 4.7× is realized with the outcome of this optimization procedure. Simulations of mask write time quantify the ability of ILT to be used for full chip applications. The optimization procedure is also applied to alternate mask technologies to reveal their advantages over commonly used 6% attenuated phase shift masks.

Double-patterning decomposition, design compliance, and verification algorithms at 32nm hp

Double patterning (DP) technology is one of the main candidates for RET of critical layers at 32nm hp. DP technology is a strong RET technique that must be considered throughout the IC design and post tapeout flows. We present a complete DP technology strategy including a DRC/DFM component, physical synthesis support and mask synthesis. In particular, the methodology contains: - A DRC-like layout DP compliance and design verification functions; - A parameterization scheme that codifies manufacturing knowledge and capability; - Judicious use of physical effect simulation to improve double-patterning quality; - An efficient, high capacity mask synthesis function for post-tapeout processing; - A verification function to determine the correctness and qualify of a DP solution; Double patterning technology requires decomposition of the design to relax the pitch and effectively allows processing with k1 factors smaller than the theoretical Rayleigh limit of 0.25. The traditional DP processes Litho-Etch-Litho- Etch (LELE) [1] requires an additional develop and etch step, which eliminates the resolution degradation which occurs in multiple exposure processed in the same resist layer. The theoretical k1 for a double-patterning technology applied to a 32nm half-pitch design using a 1.35NA 193nm imaging system is 0.44, whereas the k1 for a single-patterning of this same design would be 0.22 [2], which is sub-resolution. This paper demonstrates the methods developed at Mentor Graphics for double patterning design compliance and decomposition in an effort to minimize the impact of mask-to-mask registration and process variance. It also demonstrates verification solution implementation in the chip design flow and post-tapeout flow.

Directed self-assembly graphoepitaxy template generation with immersion lithography

Abstract. We present an optimization methodology for the template designs of subresolution contacts using directed self-assembly (DSA) with graphoepitaxy and immersion lithography. We demonstrate the flow using a 60-nm-pitch contact design in doublet with Monte Carlo simulations for DSA. We introduce the notion of template error enhancement factor (TEEF) to gauge the sensitivity of DSA printing infidelity to template printing infidelity and evaluate optimized template designs with TEEF metrics. Our data show that source mask optimization and inverse lithography technology are critical to achieve sub-80 nm non-L0 pitches for DSA patterns using 193i.

Optically induced mask critical dimension error magnification in 248 nm lithography

One form of optical proximity effect that further complicates lithography is the unexpected response of the printed image to small perturbations [critical dimension (CD) errors] in the reticle. In this way mask CD errors are actually magnified (they are reduced by less than the reduction factor of the optics) during the optical transfer to the wafer. This effect will require even tighter specifications for mask CD control when the error magnification factor is significantly above unity. The effect is particularly pronounced for tight pitches of small features, but can also impact the printing of small isolated lines. Both resist and optical nonideal responses are involved in this mask error factor (MEF). This article discussed the optical effects that produce the MEF. This article will show where the MEF due to optical effects can be ignored and where they cannot when using 248 nm lithography with a high numerical aperture (NA) tool. We will demonstrate how the NA, partial coherence, and variations in foc...

Effective model-based SRAF placement for full chip 2D layouts

Traditional SRAF placement has been governed by a generation of rules that are experimentally derived based on measurements on test patterns for various exposure conditions. But with the shrinking technology nodes, there are increased challenges in coming up with these rules. Model-based SRAF placement can help in improved overall process window, with less effort. This is true especially for two-dimensional layouts, where SRAF placement conflicts can provide a formidable challenge with varying patterns and sources. This paper investigates the trade-offs and benefits of using model-based SRAF placement over rule-based for various design configurations on a full chip. The impact on cost, time, process-window and performance will be studied. This paper will also explore the benefits and limitations of more complex free-form SRAF and OPC shapes generated by Inverse Lithography Technology (ILT), and strategies for integration into a manufacturable mask.