Kyohei Sakajiri

Inverse lithography for 45-nm-node contact holes at 1.35 numerical aperture

Inverse lithography technology (ILT) is a procedure that optimizes the mask layout to produce an image at the wafer with the targeted aerial image. For an illumination condition optimized for dense pitches, ILT inserts model-based subresolution assist features (AF) to improve the imaging of isolated features. ILT is ideal for random contact hole patterns, in which the AF are not at intuitive locations. The raw output of ILT consists of very complex smooth shapes that must be simplified for an acceptable mask write time. It is challenging for ILT to quickly converge to the ideal pattern as well as to simplify the pattern to one that can be manufactured quickly. ILT has many parameters that effect process latitude, background suppression, conversion run time, and mask write time. In this work, an optimization procedure is introduced to find the best tradeoff between image quality and run time or write time. A conversion run time reduction of 4.7× is realized with the outcome of this optimization procedure. Simulations of mask write time quantify the ability of ILT to be used for full chip applications. The optimization procedure is also applied to alternate mask technologies to reveal their advantages over commonly used 6% attenuated phase shift masks.

Physical verification and manufacturing of contact/via layers using grapho-epitaxy DSA processes

This paper extends the state of the art by describing the practical material’s challenges, as well as approaches to minimize their impact in the manufacture of contact/via layers using a grapho-epitaxy directed self assembly (DSA) process. Three full designs have been analyzed from the point of view of layout constructs. A construct is an atomic and repetitive section of the layout which can be analyzed in isolation. Results indicate that DSA’s main benefit is its ability to be resilient to the shape of the guiding pattern across process window. The results suggest that directed self assembly can still be guaranteed even with high distortion of the guiding patterns when the guiding patterns have been designed properly for the target process. Focusing on a 14nm process based on 193i lithography, we present evidence of the need of DSA compliance methods and mask synthesis tools which consider pattern dependencies of adjacent structures a few microns away. Finally, an outlook as to the guidelines and challenges to DSA copolymer mixtures and process are discussed highlighting the benefits of mixtures of homo polymer and diblock copolymer to reduce the number of defects of arbitrarily placed hole configurations.

On objectives and algorithms of inverse methods in microlithography

Inverse microlithography solves problem of finding the best mask to print target layout. We present theoretical analysis of objective functions and algorithms that are used for inversion. We analyze complexity, speed and limitations of the inverse algorithms.

Model-based SRAF insertion through pixel-based mask optimization at 32nm and beyond

SRAF insertion through inverse microlithography methodologies has been explored at length in recent years as one of the most promising approaches to determining the right placements of Model-based SRAF (MBSRAF) for complex two dimensional geometrical configurations for advanced nodes. This work will discuss the latest development of MBSRAF insertion software at Mentor Graphics. The software system operates on the principles of inverse methods of microlithography or pixel inversion. The ability to examine the image of every pixel in the work region as well as the mathematical solution to synthesize the mask shapes as a cost minimization problem make it possible to reliably deal with SRAF insertion for advanced illumination schemes such as quasar, dipole and cross-quad. Pixel inversion involving high transmission attenuated PSM as well as hard PSM will be also discussed. We will also report on the MRC capability to make the pixel inversion mask shapes manufacturable.

OPC to improve lithographic process window

Optical Proximity Correction (OPC) has become an indispensable tool used in deep sub-wavelength lithographic processes. OPC has been quite successful at reducing the linewidth dispersion across a product die, and also improving the overlapping process window of all printed features. This is achieved solely by biasing the mask features such that all print on target at the same dose. Recent advances in process window modeling, combined with highly customizable simulation and correction engines, have enabled process-aware OPC corrections. Building on these advances, the authors will describe a fast Process Window OPC (PWOPC) technique. This technique results in layouts with reduced sensitivity to defocus variations, less susceptibility to bridging and pinching failures, and greater coverage of over/underlying features (such as contact coverage by metal).

Application of pixel-based mask optimization technique for high transmission attenuated PSM

Sub-resolution assist features (SRAF) insertion using mask synthesis process based on pixel-based mask optimization schemes has been studied in recent years for various lithographical schemes, including 6% attenuated PSM (AttPSM) with off-axis illumination. This paper presents results of application of the pixelbased optimization technology to 6% and 30% AttPSM mask synthesis. We examine imaging properties of mask error enhancement factor (MEEF), critical dimension (CD) uniformity, and side-lobe printing for random contact hole patterns. We also discuss practical techniques for manipulating raw complex shapes generated by the pixel-based optimization engine that ensure mask manufacturability.

High performance ILT for hotspots repair with hierarchical pattern matching

Inverse lithography technology (ILT) has become one of the key technologies in recent years for highly optimized mask synthesis of physical layout of large scale semiconductor designs. Localized printability enhancement (LPE) has also proved useful in applying computational lithography to repair so-called hotspots to efficiently refine the designs for better process windows without re-optimizing the entire design. Although such a localized design refinement on a relatively small number of hotspots is already quite useful, in reality, it is possible that there are a large number of hotspots, thereby necessitating handling of large volume data in the repair flow. In the case of memory designs, in particular, the number of hotspots in highly repetitive patterns can be enormous, if they are counted from the flattened layout point of view. Since hotspots on repetitive patterns tend to involve processing of repeated patterns, applying pattern matching techniques becomes a natural solution such that only one instance of the repeated patterns is fully re-optimized and its result is copied and pasted over the remaining instances of the same pattern. It is also important to take advantage of the design hierarchy, because flattening of layers in repetitive hierarchical designs can result in data volume expansion that is so massive that even trivial operations such as copying and Boolean operations could become prohibitively slow. We present techniques to exploit pattern matching as well as hierarchical processing to achieve a high performance distributed hotspots reoptimization flow.

Use of ILT-based mask optimization for local printability enhancement

In this paper we study the trade-offs and benefits of using ILT-based SRAF placement/OPC over conventional SRAF placement/OPC for various front-end and back-end design configurations on a full chip. We explore the use models and benefits of using ILT-based Local Printability Enhancement (LPE) in an automated flow to eliminate hot spots that can be present on the full chip after conventional SRAF placement/OPC. We study the impact on process-window, performance, and mask manufacturability.

Optimizing gate layer OPC correction and SRAF placement for maximum design manufacturability

Sub-resolution assist features (SRAFs) or scatter bars (SBs) have steadily proliferated through IC manufacturer data preparation flows as k1 is pushed lower with each technology node. The use of this technology is quite common for gate layer at 130 nm and below, with increasingly complex geometric rules being utilized to govern the placement of SBs in proximity to target layer features. Recently, model based approaches for placement of SBs has arisen. In this work, the variety of rule-based and model-based SB options are explored for the gate layer by using new characterization and optimization functions available in the latest generation of correction and OPC verification tools. These include the ability to quantify across chip CD control with statistics on a per gate basis. The analysis includes the effects of defocus, exposure, and misalignment, and it is shown that significant improvements to CD control through the full manufacturing variability window can be realized.