Le Hong

Double pattern EDA solutions for 32nm HP and beyond

The fate of optical-based lithography hinges on the ability to deploy viable resolution enhancement techniques (RET). One such solution is double patterning (DP). Like the double-exposure technique, double patterning is a decomposition of the design to relax the pitch that requires dual masks, but unlike double-exposure techniques, double patterning requires an additional develop and etch step, which eliminates the resolution degradation due to the cross-coupling that occurs in the latent images of multiple exposures. This additional etch step is worth the effort for those looking for an optical extension [1]. The theoretical k1 for a double-patterning technique of a 32nm half-pitch (HP) design for a 1.35NA 193nm imaging system is 0.44 whereas the k1 for a single-exposure technique of this same design would be 0.22 [2], which is sub-resolution. There are other benefits to the DP technique such as the ability to add sub-resolution assist features (SRAF) in the relaxed pitch areas, the reduction of forbidden pitches, and the ability to apply mask biases and OPC without encountering mask constraints. Similarly to AltPSM and SRAF techniques one of the major barriers to widespread deployment of double patterning to random logic circuits is design compliance with split layout synthesis requirements [3]. Successful implementation of DP requires the evolution and adoption of design restrictions by specifically tailored design rules. The deployment of double patterning does spawn a couple of issues that would need addressing before proceeding into a production environment. As with any dual-mask RET application, there are the classical overlay requirements between the two exposure steps and there are the complexities of decomposing the designs to minimize the stitching but to maximize the depth of focus (DoF). In addition, the location of the design stitching would require careful consideration. For example, a stitch in a field region or wider lines is preferred over a transistor region or narrower lines. The EDA industry will be consulted for these sound automated solutions to resolve double-patterning sensitivities and to go beyond this with the coupling of their model-based and process-window applications. This work documented the resolution limitations of single exposure, and double-patterning with the latest hyper-NA immersion tools and with fully optimized source conditions. It demonstrated the best known methods to improve design decomposition in an effort to minimize the impact of mask-to-mask registration and process variance. These EDA solutions were further analyzed and quantified utilizing a verification flow.

Directed self-assembly graphoepitaxy template generation with immersion lithography

Abstract. We present an optimization methodology for the template designs of subresolution contacts using directed self-assembly (DSA) with graphoepitaxy and immersion lithography. We demonstrate the flow using a 60-nm-pitch contact design in doublet with Monte Carlo simulations for DSA. We introduce the notion of template error enhancement factor (TEEF) to gauge the sensitivity of DSA printing infidelity to template printing infidelity and evaluate optimized template designs with TEEF metrics. Our data show that source mask optimization and inverse lithography technology are critical to achieve sub-80 nm non-L0 pitches for DSA patterns using 193i.

Directed self-assembly compliant flow with immersion lithography: from material to design and patterning

Abstract. We present a directed self-assembly (DSA) compliant flow for contact/via layers with immersion lithography assuming the graphoepitaxy process for the cylinders’ formation. We demonstrate that the DSA technology enablement needs co-optimization among material, design, and lithography. We show that the number of DSA grouping constructs is countable for the gridded-design architecture. We use template error enhancement factor to choose DSA material, determine grouping design rules, and select the optimum guiding patterns. Our post-pxOPC imaging data show that it is promising to achieve two-mask solution with DSA for the contact/via layer using 193i at 5 nm node.

Model-based OPC using the MEEF matrix II

In the traditional OPC (Optical Proximity Correction) procedure, edges in a layout are broken into fragments and each fragment is iteratively adjusted by multiplying its EPE (Edge Placement Error) with a carefully selected or calculated feedback. However, the ever-shrinking technology nodes in recent years bring stronger fragment to fragment interaction. The feedback tuning approach driven by a single fragment EPE is no longer sufficient to achieve good pattern fidelity with reasonable turn-around-time. Various novel techniques such as matrix OPC [1, 2] have been developed in the past to incorporate the influence of neighboring fragments into each fragment’s movement. Here we introduce a neighboraware feedback controller for full chip level OPC applications, following the concept and algorithms of the matrix OPC that were laid out in Cobb and Granik’s work [1]. We present experimental results and discuss the benefits and challenges of the proposed feedback controller.

Directed self-assembly (DSA) grapho-epitaxy template generation with immersion lithography

In this paper, we present an optimization methodology for the template designs of sub-resolution contacts using directed self-assembly (DSA) with grapho-epitaxy and immersion lithography. We demonstrate the flow using a 60nm-pitch contact design in doublet with Monte Carlo simulations for DSA. We introduce the notion of Template Error Enhancement Factor (TEEF) to gauge the sensitivity of DSA printing infidelity to template printing infidelity, and evaluate optimized template designs with TEEF metrics. Our data shows that SMO is critical to achieve sub-80nm non- L0 pitches for DSA patterns using 193i.

Impact of process variation on 65nm across-chip linewidth variation

The latest improvements in process-aware lithography modeling have resulted in improved simulation accuracy through the dose and focus process window. This coupled with the advancements in high speed, full chip grid-based simulation provide a powerful combination for accurate process window simulation. At the 65nm node, gate CD control becomes ever more critical so understanding the amount of CD variation through the full process window is crucial. This paper will use the aforementioned simulation capability to assess the impact of process variation on ACLV (Across-Chip Linewidth Variation) and critical failures at the 65nm node. The impact of focus, exposure, and misalignment errors in manufacturing is explored to quantify both CD control and catastrophic printing failure. It is shown that there is good correlation between predicted and experimental results.

OPC for reduced process sensitivity in the double patterning flow

The pitch-splitting of patterns using the litho-etch-litho-etch double patterning technique (DPT) may be required at the 22nm node. By splitting the layout into 2 masks, DPT introduces some new potential failure mechanisms. These new failure mechanisms can occur if the layer decomposition and subsequent OPC fail to account for interlayer misalignment and corner rounding of the decomposed masks. This paper will suggest novel solutions which can be taken during the OPC step to account of interlayer misalignment and corner rounding at decomposed edges. These methods will be shown to produce improved process window and reduced sensitivity to misalignment compared to a conventional OPC without interlayer awareness.

Design technology co-optimization (DTCO) study on self-aligned-via (SAV) with Lamella DSA for sub-7 nm technology

In this paper, we present a design technology co-optimization (DTCO) flow to pattern self-aligned via (SAV) using two masks with grapho-epitaxy of lamella BCP and 193i for sub-7nm design. We show that it is necessary to consider both metal and via layers at the same time in creating design rules with process variations. Due to lamella DSA’s own characteristics, it can be easily applied in dense memory or SRAM applications for SAV patterning using traditional single-material metal hard mask. However, to achieve two-mask SAV solution for logic applications, we need to apply alternating hard mask in metal to cut lamella DSA patterns without compromising the technology scaling.

Directed Self Assembly (DSA) compliant flow with immersion lithography: from material to design and patterning

In this paper, we present a DSA compliant flow for contact/via layers with immersion lithography assuming the grapho-epitaxy process for cylinders’ formation. We demonstrate that the DSA technology enablement needs co-optimization among material, design, and lithography. We show that the number of DSA grouping constructs is countable for the gridded-design architecture. We use Template Error Enhancement Factor (TEEF) to choose DSA material, determine grouping design rules, and select the optimum guiding patterns. Our post-pxOPC imaging data shows that it is promising to achieve 2-mask solution with DSA for the contact/via layer using 193i at 5nm node.

Novel method for optimizing lithography exposure conditions using full-chip post-OPC simulation

At 65 nm and below, full-chip verification of OPC is done for nominal dose and focus, as well as for process corners representing a two-to-three sigma deviation from the manufacturing setpoints. Such an approach interrogates the intersection of design layout with process variation to elucidate specific locations which will tend to be yield-limiting in manufacturing. With vanishingly small margins between allowable process windows and real in-fab variability, it is of utmost importance to optimize the critical exposure parameters such as projection optic numerical aperture, illumination source mode and sigma, and source polarization. The traditional approach to optimizing these exposure conditions has involved selecting representative feature test patterns (such as 1D lines at multiple pitches, or memory cells), placing simulation cutlines across selected locations, establishing allowable CD tolerances, and calculating overlapping process windows for all cutlines of interest. Such approaches are to first order effective in coarse tuning exposure conditions, but underutilize the rich information content which is available from todays rapid large-area post-OPC simulation engines. We report here on the use of full-chip post-OPC simulation and error checking in conjunction with illumination optimization tooling to provide a more thorough and versatile statistical analysis capability. It is shown that the new method proposed here results in a more robust process window than that which would be obtained by the conditions selected using the traditional optimization method.