Srividya Jayaram

Effective model-based SRAF placement for full chip 2D layouts

Traditional SRAF placement has been governed by a generation of rules that are experimentally derived based on measurements on test patterns for various exposure conditions. But with the shrinking technology nodes, there are increased challenges in coming up with these rules. Model-based SRAF placement can help in improved overall process window, with less effort. This is true especially for two-dimensional layouts, where SRAF placement conflicts can provide a formidable challenge with varying patterns and sources. This paper investigates the trade-offs and benefits of using model-based SRAF placement over rule-based for various design configurations on a full chip. The impact on cost, time, process-window and performance will be studied. This paper will also explore the benefits and limitations of more complex free-form SRAF and OPC shapes generated by Inverse Lithography Technology (ILT), and strategies for integration into a manufacturable mask.

Automatic SRAF size optimization during OPC

Sub-resolution assist features (SRAFs) are a common addition to low-k1 masks to improve process window for isolated features. Traditional SRAF placement, which has been widely adopted by the industry, is governed by generation of rules which have been experimentally derived based on exposure and measurement of test patterns. The placement rules must generate SRAFs large enough to improve the process window, but small enough not to print at any point within that process window. This has resulted in tremendous challenges to meet the cost and process window requirements for the advanced technology nodes. Specifically, in the logic products, due to the complex two-dimensional patterns, the placement rules will be quite challenging in order to ensure maximum sizing and no printing. SRAF generation is also plagued by over clean-up due to mask rule checks (MRC) specified. The challenge is to derive the best rules which generate SRAFs without printing through the process window. This paper will explore the possibility of an alternate SRAF placement methodology where the SRAF placement rules can be greatly simplified, and SRAF printability through the required process window conditions will automatically be accounted for during a subsequent Optical Proximity Correction (OPC) step. This methodology has the advantages of simplifying the placement rules while simultaneously ensuring maximum possible SRAF size with no printing within the process window. The SRAF size optimization is performed concurrently with OPC thereby saving valuable time on trying to optimize the rule deck. In this method the side-lobes are automatically suppressed well under the imaging threshold. Experimental verification of the SRAF dependence on its sizing and placement along with printability and main-feature process window will be demonstrated.

Automatic assist feature placement optimization based on process-variability reduction

To maximize the process window and CD control of main features, sizing and placement rules for sub-resolution assist features (SRAF) need to be optimized, subject to the constraint that the SRAFs not print through the process window. With continuously shrinking target dimensions, generation of traditional rule-based SRAFs is becoming an expensive process in terms of time, cost and complexity. This has created an interest in other rule optimization methodologies, such as image contrast and other edge- and image-based objective functions. In this paper, we propose using an automated model-based flow to obtain the optimal SRAF insertion rules for a design and reduce the time and effort required to define the best rules. In this automated flow, SRAF placement is optimized by iteratively generating the space-width rules and assessing their performance against process variability metrics. Multiple metrics are used in the flow. Process variability (PV) band thickness is a good indicator of the process window enhancement. Depth of focus (DOF), the total range of focus that can be tolerated, is also a highly descriptive metric for the effectiveness of the sizing and placement rules generated. Finally, scatter bar (SB) printing margin calculations assess the allowed exposure range that prevents scatter bars from printing on the wafer.

The PIXBAR OPC for contact-hole pattern in sub-70-nm generation

As semiconductor technologies move toward 70nm generation and below, contact-hole is one of the most challenging features to print on wafer. There are two principle difficulties in defining small contact-hole patterns on wafer. One is insufficient process margin besides poor resolution compared with line-space pattern. The other is that contact-hole should be made through pitches and random contact-hole pattern should be fabricated from time to time. PIXBAR technology is the candidate which can help improve the process margin for random contact-holes. The PIXBAR technology lithography attempts to synthesize the input mask which leads to the desired output wafer pattern by inverting the forward model from mask to wafer. This paper will use the pixel-based mask representation, a continuous function formulation, and gradient-based interactive optimization techniques to solve the problem. The result of PIXBAR method helps gain improvement in process window with a short learning cycle in contact-hole pattern assist-feature testing.

Influence of the illumination source on model-based SRAF placement

Sub-Resolution Assist Features (SRAFs) have been extensively used to improve the process margin for isolated and semi-isolated features. It has been shown that compared to rule-based SRAFs, model-based placement of SRAFs can result in better overall process window. Various model-based approaches have been reported to affect SRAF placements. Even with model-based solutions, the complexity of two-dimensional layouts results in SRAF placement conflicts, producing numerous challenges to optimal SRAF placement for each pattern configuration. Furthermore, tuning of SRAF placement algorithms becomes challenging with varying patterns and sources [1-3]. Recently, pixelated source in optical lithography has become the subject of increased exploration to enable 22/20 nm technology nodes and beyond. Optimization of the illumination shape, including free-form pixelated sources, has shown performance gains, compared to standard source shapes [4-6]. This paper will demonstrate the influence of such different free-form sources as well as conventional sources on model-based SRAF placement. Typically in source optimization, the selection of the optimization patterns is exigent since it drives the source solution. Small differences in the selected patterns produce subtle changes in the optimized source shapes. It has also been previously reported that SRAF placements are significantly dependent on the illumination [1]. In this paper, the impact of changes in the design and/or source optimization patterns on the optimized source and hence on the SRAF placement is reported. Variations in SRAF placements will be quantified as a function of change in the free-form sources. Lithographic performance of the different SRAF placement schema will be verified using simulation.

Impact of illumination on model-based SRAF placement for contact patterning

Sub-Resolution Assist Features (SRAFs) have been used extensively to improve the process latitude for isolated and semi-isolated features in conjunction with off-axis illumination. These SRAFs have typically been inserted based upon rules which assign a global SRAF size and proximity to target shapes. Additional rules govern the relationship of assist features to one another, and for random logic contact layers, the overall ruleset can become rather complex. It has been shown that model-based placement of SRAFs for contact layers can result in better worst-case process window than that obtained with rules, and various approaches have been applied to affect such placement. The model comprehends the specific illumination being used, and places assist features according to that model in the optimum location for each contact hole. This paper examines the impact of various illumination schemes on model-based SRAF placement, and compares the resulting process windows. Both standard illumination schemes and more elaborate pixel-based illumination pupil fills are considered.

Novel method for optimizing lithography exposure conditions using full-chip post-OPC simulation

At 65 nm and below, full-chip verification of OPC is done for nominal dose and focus, as well as for process corners representing a two-to-three sigma deviation from the manufacturing setpoints. Such an approach interrogates the intersection of design layout with process variation to elucidate specific locations which will tend to be yield-limiting in manufacturing. With vanishingly small margins between allowable process windows and real in-fab variability, it is of utmost importance to optimize the critical exposure parameters such as projection optic numerical aperture, illumination source mode and sigma, and source polarization. The traditional approach to optimizing these exposure conditions has involved selecting representative feature test patterns (such as 1D lines at multiple pitches, or memory cells), placing simulation cutlines across selected locations, establishing allowable CD tolerances, and calculating overlapping process windows for all cutlines of interest. Such approaches are to first order effective in coarse tuning exposure conditions, but underutilize the rich information content which is available from todays rapid large-area post-OPC simulation engines. We report here on the use of full-chip post-OPC simulation and error checking in conjunction with illumination optimization tooling to provide a more thorough and versatile statistical analysis capability. It is shown that the new method proposed here results in a more robust process window than that which would be obtained by the conditions selected using the traditional optimization method.

Lithographic benefits and mask manufacturability study of curvilinear masks

As the EUV lithography is extending beyond 7nm technology, design to mask strategy becomes more complex. New challenges including advanced OPC and ILT in mask optimization, curvilinear masks, shrinking Mask Rule Checking (MRC), Sub-Resolution Assist Features (SRAF) generation and formation, and other complex mask geometries drive the needs to study this synergy from different stages of the flow from Optical Proximity Correction (OPC), Mask Process Correction (MPC), fracturing, to mask writing and inspection. In this study, different OPC and SRAF mask formations including curvilinear masks, controlled Manhattanized approximations of curvilinear masks, and conventional masks are generated. We illustrate whether curvilinear masks have any demonstrable lithographic benefits. A quantitative comparison of how the Manhattanization impacts mask formation. The image quality metrics such as Image Log Slope (ILS), Process Viability (PV) Band, and Depth of Focus (DOF) from various OPC mask flavors including different MRC settings and different mask forms are compared and discussed. The mask manufacturability study is conducted to identify any major challenges and approaches to minimize, including assessing the value and need for native curvilinear write tool support on a MultiBeam Mask Writer (MBMW) or a single beam Vector Shaped Beam (VSB) mask writer.

EUV implementation of assist features in contact patterns

As feature sizes become smaller and smaller, the complexity and the cost of using multiple patterning with 193i becomes a significant issue in lithography. Hence, EUV starts to play an important role for 7nm node and beyond. Industry is now investigating solutions on all major EUV components – source, resist mask technology, as well as resolution enhancement techniques (RET), including sub-resolution assist features (SRAFs). Unlike ArF lithography, the non-telecentricity of the EUV optical system coupled with the relatively thick mask stack causes shadowing effects. This asymmetric imaging may in turn have an impact on assist feature placement, requiring different SRAF rules for different directions at the edges and corners. In this work, simulation studies were conducted using Calibre on 20x20 nm contact patterns through pitch to investigate the impact of assist features. Assist features were varied as a function of horizontal / vertical positions independently and the image quality parameters such as depth of focus (DOF), MEEF, best focus (BF) shift and overlapping process window were monitored with and without SRAFs. Both rules-based and model based assist feature placements were implemented for selected patterns. Results indicate that inclusion of assist features for contact arrays improve individual and overlapping process windows with minimal effect on best focus shift. Wafer data collected from these patterns confirmed the improvement in overlapping process window with the inclusion of assist features.

Effective conflict resolution strategies for SRAF placement

Sub-Resolution Assist Features (SRAFs) have emerged as a key technology to enable semiconductor manufacturing for advanced technology nodes. SRAF placement is required to adhere to manufacturability constraints (MRC). MRC specifications are distance and size constraints specified by the user to ensure SRAFs are not detrimental to the final target shapes being printed. Conceptually, SRAF placement can be divided into two steps - SRAF candidate generation and SRAF candidate cleanup or conflict resolution. SRAFs generated as candidates may not adhere to MRC constraints. It is during the cleanup/conflict resolution process that the MRC constraints are enforced. In this paper we focus on the latter phase - cleanup. The goal of the cleanup phase is to retain as much of the initial candidates as possible, and, if necessary, transform them to adhere to MRC conditions. An SRAF is said to be in conflict with another shape if it violates the distance MRC constraint. One can model these conflicts using a conflict graph G=(V,E), whose vertices V correspond to geometric shapes involved in a conflict and an edge is present in E, between two vertices if the corresponding shapes are involved in a conflict. A weight is associated with each vertex that could, for example, correspond to area of the corresponding shape. The goal of conflict resolution then, is to find a transformation of the vertices so that the resulting graph is conflict free while maximizing the weight of vertices retained. This can be viewed as a generalization of the computationally hard problem of finding the largest independent set of candidates, albeit allowing for transformation. The transformations we allow include deletion, splitting, resizing, merge, and bounded translation. In this paper, we describe an approach which classifies the conflicts and apply appropriate transformations to achieve effective SRAF placement. Further, we demonstrate that such a strategy reduces the number of rules to be specified by the user, reducing the user effort needed to achieve desirable imaging results.