James Word

Challenges and opportunities in applying grapho-epitaxy DSA lithography to metal cut and contact/via applications

Directed self assembly has become a very attractive technology for Fin and contact/via applications. Some of the issues related to pattern placement error, defectivity rates and process integration are actively being addressed by the industry and have not faced significant roadblocks for contact-hole applications. While many DSA applications have been proposed, deploying DSA for Fin structures competes in cost and variability control with SADP techniques. Given the 1D nature of find structures, it is difficult to control fin placement with accuracy better than 4nm 3 sigma. In addition, a second patterning step is needed to remove the un-wanted sections of the grating and leaving behind only the required fin structures, therefore limiting its adoption. On the other hand, DSA applied to contact/via holes has demonstrated low defectivity rates due to improved polymerization and processing techniques, as well as an adequate control to reduce the placement error due to thermal fluctuations during the annealing and cylinder formation process. For that reason, the results from contact/via layers can extend to the metal cut layer printing with DSA grapho-epitaxy. In this paper, we show that DSA provides a promising cost-effective solution for the technology scaling by reducing mask number from N to N-1. It is shown that pxOPC may provide better guiding patterns than the conventional one. In addition, the practical grouping rules for DSA should avoid 2D grouping, avoid putting more than 3 features in a group with different pitches, and avoid grouping features with different sizes. Our recommendations to designers for DSA technology are the following: if the design is to be decomposed with 2 or more DSA masks, then the design rules should be set up in this way: first the minimum pitch is better to be on DSA material’s own natural pitch; second, for each DSA mask, singletons and bar-like grouping shapes with DSA’s natural pitch should be used as much as possible.

Flare in extreme ultraviolet lithography: metrology, out-of-band radiation, fractal point-spread function, and flare map calibration

The critical role of flare in extreme ultraviolet (EUV) lithography is well known. In this work, the implementation of a robust flare metrology is discussed, and the proposed approach is qualified both in terms of precision and accuracy. The flare measurements are compared to full-chip simulations using a simplified single fractal point-spread function (PSF), and the parameters of the analytical PSF are optimized by comparing the simulation output to the experimental results. After flare map calibration, the matching of simulation and experiment in the flare range from 4 to 12% is quite good, clearly indicating an offset of about 3%. The origin of this offset is attributed to the presence of DUV light. An experimental estimate of the DUV component is found in good agreement with the predicted value.

Layout compensation for EUV flare

Flare has been noted as a significant concern for Extreme Ultraviolet (EUV) Lithography. Recent results on prototype tools have shown flare on the order of 40% in extreme cases. This is far from the ideal result. Flare compensation for EDA software tools such as Mentor Graphics’ Calibre RET Suite has been developed, and can be used to compensate density dependent fluctuations in conventional DUV lithography. This can be as simple as making corrections using rules for the variations of isolated and dense lines in an environment with prescribed flare, or a more complex correction incorporating flare into model-based OPC. Flare in EUV systems, however, has been shown to be non-uniform, with complex variations. In this presentation, we describe this flare correction technique and explore the correction of typical IC layouts that would be required to compensate for reported EUV flare values.

Considerations for the use of defocus models for OPC

It has been published that there is potential benefit to utilizing an OPC model based upon defocus instead of best focus processing, to give more robust patterning. While this is true with respect to gross opens and bridging problems, the available CD budget and the anticipated manufacturing consumption of defocus budgets must be considered. The net result will almost certainly always be that for gate layer processing, defocus model based OPC is not desirable. For other layers there may be favorable yield implications to running in such a manner, but the average CD in manufacturing will deviate from the design target. This paper will explore the interplay between variable focus distributions in manufacturing and the required CD control, pointing to those conditions under which a defocus model is advisable, and where it is not. Furthermore, the optimum magnitude of defocus is a compromise and has implications for final electrical performance.

Advanced layout fragmentation and simulation schemes for model-based OPCC

Traditional model based OPC software operates under a set of simple guiding principles. First, a design is fragmented into finitely sized segments, the sizes and numbers of which are limited by run-time and mask constraints. Within each fragment the intensity profile (aerial image) and edge-placement error (EPE) are calculated at a single location. Finally, the length of the entire fragment is moved to correct for the EPE at that location. This scheme has potential limitations in certain cases. For instance, cases where the aerial image contour (and therefore EPE) vary at a higher frequency than the minimum allowed fragmentation frequency. This so-called aerial image ripple problem can challenge the abilities of simple model based OPC. In addition, certain advanced RET schemes require that EPE be controlled in areas that have no adjacent mask polygon. Similarly, certain double-exposure RETs require the mutual optimization of features on multiple mask layers. Our paper will describe a flexible model based OPC scheme called Matrix OPC, which has proven capabilities of resolving these and many other advanced RET problems.

Directed self-assembly graphoepitaxy template generation with immersion lithography

Abstract. We present an optimization methodology for the template designs of subresolution contacts using directed self-assembly (DSA) with graphoepitaxy and immersion lithography. We demonstrate the flow using a 60-nm-pitch contact design in doublet with Monte Carlo simulations for DSA. We introduce the notion of template error enhancement factor (TEEF) to gauge the sensitivity of DSA printing infidelity to template printing infidelity and evaluate optimized template designs with TEEF metrics. Our data show that source mask optimization and inverse lithography technology are critical to achieve sub-80 nm non-L0 pitches for DSA patterns using 193i.

EUV flare and proximity modeling and model-based correction

The introduction of EUV lithography into the semiconductor fabrication process will enable a continuation of Moores law below the 22 nm technology node. EUV lithography will, however, introduce new and unwanted sources of patterning distortions which must be accurately modeled and corrected on the reticle. Flare caused by scattered light in the projection optics is expected to result in several nanometers of on-wafer dimensional variation, if left uncorrected. Previous work by the authors has focused on combinations of model-based and rules-based approaches to modeling and correction of flare in EUV lithography. Current work to be presented here focuses on the development of an all model-based approach to compensation of both flare and proximity effects in EUV lithography. The advantages of such an approach in terms of both model and OPC accuracy will be discussed. In addition, the authors will discuss the benefits and tradeoffs associated with hybrid OPC approaches which mix both rules-based and modelbased OPC. The tradeoffs to be explored include correction time, accuracy, and data volume.

Inverse vs. traditional OPC for the 22nm node

The 22nm node will be patterned with very challenging Resolution Enhancement Techniques (RETs) such as double exposure or double patterning. Even with those extreme RETs, the k1 factor is expected to be less than 0.3. There is some concern in the industry that traditional edge-based simulate-then-move Optical Proximity Correction (OPC) may not be up to the challenges expected at the 22nm node. Previous work presented the advantages of a so-called inverse OPC approach when coupled with extreme RETs or illumination schemes. The smooth mask contours resulting from inverse corrections were shown not to be limited by topological identity, feedback locality, or fragment conformity. In short, inverse OPC can produce practically unconstrained and often non-intuitive mask shapes. The authors will expand this comparison between traditional and inverse OPC to include likely 22nm RETs such as double dipole lithography and double patterning, comparing dimensional control through process window for each OPC method. The impact of mask simplification of the inverse OPC shapes into shapes which can be reliably manufactured will also be explored.

Effective model-based SRAF placement for full chip 2D layouts

Traditional SRAF placement has been governed by a generation of rules that are experimentally derived based on measurements on test patterns for various exposure conditions. But with the shrinking technology nodes, there are increased challenges in coming up with these rules. Model-based SRAF placement can help in improved overall process window, with less effort. This is true especially for two-dimensional layouts, where SRAF placement conflicts can provide a formidable challenge with varying patterns and sources. This paper investigates the trade-offs and benefits of using model-based SRAF placement over rule-based for various design configurations on a full chip. The impact on cost, time, process-window and performance will be studied. This paper will also explore the benefits and limitations of more complex free-form SRAF and OPC shapes generated by Inverse Lithography Technology (ILT), and strategies for integration into a manufacturable mask.

Full-chip-model-based correction of flare-induced linewidth variation

Scattered light in optical lithography, also known as flare, has been shown to cause potentially significant linewidth variation at low-k1 values. The interaction radius of this effect can extend essentially from zero to the full range of a product die and beyond. Because of this large interaction radius the correction of the effect can be very computation-intensive. In this paper, we will present the results of our work to characterize the flare effect for 65nm and 90nm poly processes, model that flare effect as a summation of gaussian convolution kernels, and correct it within a hierarchical model based OPC engine. Novel methods for model based correction of the flare effect, which preserve much of the design hierarchy, is discussed. The same technique has demonstrated the ability to correct for long-range loading effects encountered during the manufacture of reticles.