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Dive into the research topics where Alexandre M. Amory is active.

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Featured researches published by Alexandre M. Amory.


international test conference | 2005

A scalable test strategy for network-on-chip routers

Alexandre M. Amory; Eduardo Wenzel Brião; Érika F. Cota; Marcelo Lubaszewski; Fernando Gehm Moraes

Network-on-chip has recently emerged as alternative communication architecture for complex system chip and different aspects regarding NoC design have been studied in the literature. However, the test of the NoC itself for manufacturing faults has been marginally tackled. This paper proposes a scalable test strategy for the routers in a NoC, based on partial scan and on an IEEE 1500-compliant test wrapper. The proposed test strategy takes advantage of the regular design of the NoC to reduce both test area overhead and test time. Experimental results show that a good tradeoff of area overhead, fault coverage, test data volume, and test time is achieved by the proposed technique. Furthermore, the method can be applied for large NoC sizes and it does not depend on the network routing and control algorithms, which makes the method suitable to test a large class of network models


IEEE Transactions on Computers | 2008

A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip

Érika F. Cota; Fernanda Lima Kastensmidt; Maico Cassel; Marcos Herve; P. Meirelles; Alexandre M. Amory; Marcelo Lubaszewski

A novel strategy to detect interconnect faults between distinct channels in networks-on-chip is proposed. Short faults between distinct channels in the data, control and communication handshake lines are considered in a cost-effective test sequence for Mesh NoC topologies based on XY routing.


european test symposium | 2006

Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism

Alexandre M. Amory; Kees Goossens; Erik Jan Marinissen; Marcelo Lubaszewski; Fernando Gehm Moraes

This paper proposes a wrapper design for interconnects with guaranteed bandwidth and latency services and on-chip protocol. We demonstrate that these interconnects abstract the interconnect details and provide predictability in the data transfer, which are desirable not only for the functional domain but also for the test application. The proposed wrapper is implemented in VHDL and integrated to the Ethereal NoC. The results show the impact of bandwidth in the core test time. The wrapper area and core test time are compared with a wrapper design for dedicated TAM


design, automation, and test in europe | 2013

Topology-agnostic fault-tolerant NoC routing method

Eduardo Wächter; Augusto Erichsen; Alexandre M. Amory; Fernando Gehm Moraes

Routing algorithms for NoCs were extensively studied in the last 12 years, and proposals for algorithms targeting some cost function, as latency reduction or congestion avoidance, abound in the literature. Fault-tolerant routing algorithms were also proposed, being the table-based approach the most adopted method. Considering SoCs with hundred of cores in a near future, features as scalability, reachability, and fault assumptions should be considered in the fault-tolerant routing methods. However, the current proposals some have some limitations: (1) increasing cost related to the NoC size, compromising scalability; (2) some healthy routers may not be reached even if there is a source-target path; (3) some algorithms restricts the number of faults and their location to operate correctly. The present work presents a method, inspired in VLSI routing algorithms, to search the path between source-target pairs where the network topology is abstracted. Results present the routing path for different topologies (mesh, torus, Spidergon and Hierarchical-Spidergon) in the presence of faulty routers. The silicon area overhead and total execution time of the path computation is small, demonstrating that the proposed method may be adopted in NoC designs.


symposium on integrated circuits and systems design | 2011

Multi-task dynamic mapping onto NoC-based MPSoCs

Marcelo Mandelli; Alexandre M. Amory; Luciano Ost; Fernando Gehm Moraes

Task mapping defines the best placement of a given task in the MPSoC, according to some criteria, as energy or Manhattan distance minimization. The ITRS roadmap forecast in a near future MPSoCs with hundreds of processing elements (PEs). Therefore, dynamic mapping heuristics are required. An important gap is observed in the mapping literature: the lack of proposals targeting multi-task dynamic mapping. In this context, the present work proposes an energy-aware dynamic task mapping heuristic, allowing multiple tasks allocation per PE. Experimental results are executed in an actual MPSoC running distributed applications. Comparing a single-task to the multi-task mapping, the energy spent in the NoC is reduced in average by 51% (best case: 72%), with an average execution time overhead of 18%. Besides the communication energy reduction, the multi-task mapping enables a greater number of applications executing simultaneously, or smaller MPSoCs, which reduces the system cost.


vlsi test symposium | 2007

DfT for the Reuse of Networks-on-Chip as Test Access Mechanism

Alexandre M. Amory; Frederico Ferlini; Marcelo Lubaszewski; Fernando Gehm Moraes

This paper presents new DfT modules required to use networks-on-chip as test access mechanism. The paper demonstrates that the proposed DfT modules can be also implemented on top of low cost networks-on-chip, i.e. networks without complex services. The DfT modules, which consist of test wrappers and test pin interfaces, are designed such that both the tester and CUTs transport test data unaware of the network. The DfT modules was analysed in terms of silicon area and test time, considering different network and test configurations.


symposium on integrated circuits and systems design | 2001

Using the CAN protocol and reconfigurable computing technology for Web-based smart house automation

Fernando Gehm Moraes; Alexandre M. Amory; Ney Laert Vilar Calazans; Eduardo Augusto Bezerra; Juracy Petrini

Abstract: This paper presents the hardware implementation of a multiplatform control system for house automation using FPGAs. Such a system belongs to a domain usually named domotics or smart house systems. The approach combines hardware and software technologies. The system is controlled through the Internet and the home devices being connected use the CAN control protocol. Users can remotely control their houses using a web browser (Client). Locally, instructions received from the Client are translated by the Server, which distributes the commands to the domestic appliances. The implemented system has the following characteristics, which distinguish it from existing approaches: (i) the client interface is automatically updated; (ii) a standard communication protocol (CAN) is used in the hardware implementation, providing reliability and error control; (iii) new appliances are easily inserted in the system; (iv) system security is provided by user authentication; (v) user rights can be set up by an administration interface.


international test conference | 2007

Redefining and testing interconnect faults in Mesh NoCs

Érika F. Cota; Fernanda Lima Kastensmidt; Maico Cassel; Paulo Meirelles; Alexandre M. Amory; Marcelo Lubaszewski

An extended fault model and novel strategy to tackle interconnect faults in network-on-chips are proposed. Short faults between distinct channels are considered in a cost-effective test sequence for mesh NoC topologies based on XY routing.


Journal of Parallel and Distributed Computing | 2011

A new test scheduling algorithm based on Networks-on-Chip as Test Access Mechanisms

Alexandre M. Amory; Cristiano Lazzari; Marcelo Lubaszewski; Fernando Gehm Moraes

Networks-on-Chip (NoCs) can be used for test data transportation during manufacturing tests. On one hand, NoC can avoid dedicated Test Access Mechanisms (TAMs), reducing long global wires, and potentially simplifying the layout. On the other hand, (a) it is not known how much wiring is saved by reusing NoCs as TAMs, (b) the impact of reuse-based approaches on test time is not clear, and (c) a computer aided test tool must be able to support different types of NoC designs. This paper presents a test environment where the designer can quickly evaluate wiring and test time for different test architectures. Moreover, this paper presents a new test scheduling algorithm for NoC TAMs which does not require any NoC timing detail and it can easily model NoCs of different topologies. The experimental results evaluate the proposed algorithm for NoC TAMs with an exiting algorithm for dedicated TAMs. The results demonstrate that, on average, 24% (up to 58%) of the total global wires can be eliminated if dedicated TAMs are not used. Considering the reduced amount of dedicated test resources with NoC TAM, the test time of NoC TAM is only, on average, 3.88% longer compared to dedicated TAMs.


international on-line testing symposium | 2000

Estimating circuit fault-tolerance by means of transient-fault injection in VHDL

Fabian Vargas; Alexandre M. Amory

We present a new approach to estimate the reliability of complex circuits used in harmful radiation environments. This goal can be attained in an early stage of the design process. Usually, this step is performed in laboratory, by means of radiation facilities (particle accelerators). In our case, we estimate the expected tolerance of the complex circuit with respect to SEU during the VHDL specification step. By doing so, the early-estimated reliability level is used to balance the design process into a trade-off between maximum area overhead due to the insertion of redundancy and the minimum reliability required for a given application. This approach is being automated through the development of a CAD tool.

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Dive into the Alexandre M. Amory's collaboration.

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Fernando Gehm Moraes

Pontifícia Universidade Católica do Rio Grande do Sul

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Marcelo Lubaszewski

Universidade Federal do Rio Grande do Sul

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Érika F. Cota

Universidade Federal do Rio Grande do Sul

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Eduardo Wächter

Pontifícia Universidade Católica do Rio Grande do Sul

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Felipe A. Kuentzer

Pontifícia Universidade Católica do Rio Grande do Sul

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Leonardo Rezende Juracy

Pontifícia Universidade Católica do Rio Grande do Sul

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César A. M. Marcon

Pontifícia Universidade Católica do Rio Grande do Sul

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Ney Laert Vilar Calazans

Pontifícia Universidade Católica do Rio Grande do Sul

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Augusto Erichsen

Pontifícia Universidade Católica do Rio Grande do Sul

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Matheus T. Moreira

Pontifícia Universidade Católica do Rio Grande do Sul

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