Érika F. Cota

A scalable test strategy for network-on-chip routers

Network-on-chip has recently emerged as alternative communication architecture for complex system chip and different aspects regarding NoC design have been studied in the literature. However, the test of the NoC itself for manufacturing faults has been marginally tackled. This paper proposes a scalable test strategy for the routers in a NoC, based on partial scan and on an IEEE 1500-compliant test wrapper. The proposed test strategy takes advantage of the regular design of the NoC to reduce both test area overhead and test time. Experimental results show that a good tradeoff of area overhead, fault coverage, test data volume, and test time is achieved by the proposed technique. Furthermore, the method can be applied for large NoC sizes and it does not depend on the network routing and control algorithms, which makes the method suitable to test a large class of network models

The impact of NoC reuse on the testing of core-based systems

The authors propose the reuse of on-chip networks for the test of core-based systems that use this platform. Two possibilities of reuse are proposed and discussed with respect to test time minimization. An algorithm exploiting network characteristics to reduce test time is presented. Experimental results show that the parallelization capability of the network can be exploited to reduce the system test time, whereas area and pin overhead are strongly minimized.

A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip

A novel strategy to detect interconnect faults between distinct channels in networks-on-chip is proposed. Short faults between distinct channels in the data, control and communication handshake lines are considered in a cost-effective test sequence for Mesh NoC topologies based on XY routing.

Dependable Network-on-Chip Router Able to Simultaneously Tolerate Soft Errors and Crosstalk

As the technology scales down into deep sub-micron domain, more IP cores are integrated in the same die and new communication architectures are used to meet performance and power constraints. However, the same technologic advance makes devices and interconnects more sensitive to new types of malfunctions and failures, such as crosstalk and transient faults. This paper proposes fault tolerant techniques to protect NoC routers against the occurrence of soft errors and crosstalk at the same time, with minimum area and performance overhead. Experimental results show that a cost-effective protection alternative can be achieved by the combination of error correction codes and time redundancy techniques

Improving yield of torus nocs through fault-diagnosis-and-repair of interconnect faults

We propose a fault tolerance method for torus NoCs capable of increase the yield with minimal performance overhead. The proposed approach consists in detecting and diagnosing interconnect faults using BIST structures and activating alternative paths for the faulty links. Experimental results show that alternative fault-free paths are found by the dynamic routing for 95% of the diagnosed faults (stuck-at and pairwise shorts within a single link or between any two links).

Evaluating SEU and crosstalk effects in network-on-chip routers

This work intends to evaluate the effect of a single event upsets (SEUs) and crosstalk faults in a NoC router architecture by developing a fault injection mechanism, allowing an accurate analysis of the impact of SEU and crosstalk over the router service. Results show that such faults may affect the router behavior, causing loss of packets, errors in packet information or even compromising the router service, provoking permanent routing problems

FAULT SIMULATION OF MEMS USING HDLS

This paper describes an approach to fault simulation of MEMS using an analog Hardware Description Language (HDL). HDL languages facilitate the description of mixed-domain devices, providing powerful representation capabilities which are not limited to the use of the traditional equivalent electrical modes. This is exploited in this paper for fault simulation of MEMS, showing the advantages of using an HDL for this task. An electro-thermal converter is used as test vehicle, for which an equivalent electrical more is readily obtained. Typical defects and failure mechanisms which can affect these devices fabricated using CMOS-compatible bulk micromachining are shown. These defects are used for illustrating the fault simulation approach which appears to be more comprehensive and systematic than previous approaches.

Concurrent test of Network-on-Chip interconnects and routers

In this work, a functional-based test method is presented that integrates the test of Network-on-Chip interconnects and routers. The proposed approach is scalable to any size of network. Experimental results show that fault coverage can reach up to 100% of interconnect faults and 92.75% of router faults, with yet affordable test sequence lengths.

A new adaptive analog test and diagnosis system

This paper presents a low-cost analog test system with diagnosis capabilities. The tester is able to detect faults in any linear circuit by learning a reference circuit behavior in a first step, and comparing this behavior against the output of the circuit under test in a second step. For a faulty circuit, a third step takes place to locate the fault. The diagnosis method consists in injecting probable faults in a mathematical model of the circuit, and later comparing its output with the output of the real faulty circuit. This system has been successfully applied to a case study, a biquad filter. Soft, large, and hard deviations on components, as well as faults in operational amplifiers, were considered. Experimental results have proven the feasibility and efficiency of the proposed test and diagnosis system.

Microsystems testing: an approach and open problems

In this work a Computer-Aided Testing (CAT) tool is proposed that brings a systematic way of dealing with testing problems in emerging microsystems. Experiments with case-studies illustrate the techniques and tools embedded in the CAT environment. Some of the open problems that shall be addressed in the near future as an extension to this work are also discussed.