Marcelo Lubaszewski

A scalable test strategy for network-on-chip routers

Network-on-chip has recently emerged as alternative communication architecture for complex system chip and different aspects regarding NoC design have been studied in the literature. However, the test of the NoC itself for manufacturing faults has been marginally tackled. This paper proposes a scalable test strategy for the routers in a NoC, based on partial scan and on an IEEE 1500-compliant test wrapper. The proposed test strategy takes advantage of the regular design of the NoC to reduce both test area overhead and test time. Experimental results show that a good tradeoff of area overhead, fault coverage, test data volume, and test time is achieved by the proposed technique. Furthermore, the method can be applied for large NoC sizes and it does not depend on the network routing and control algorithms, which makes the method suitable to test a large class of network models

The impact of NoC reuse on the testing of core-based systems

The authors propose the reuse of on-chip networks for the test of core-based systems that use this platform. Two possibilities of reuse are proposed and discussed with respect to test time minimization. An algorithm exploiting network characteristics to reduce test time is presented. Experimental results show that the parallelization capability of the network can be exploited to reduce the system test time, whereas area and pin overhead are strongly minimized.

A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip

A novel strategy to detect interconnect faults between distinct channels in networks-on-chip is proposed. Short faults between distinct channels in the data, control and communication handshake lines are considered in a cost-effective test sequence for Mesh NoC topologies based on XY routing.

Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism

This paper proposes a wrapper design for interconnects with guaranteed bandwidth and latency services and on-chip protocol. We demonstrate that these interconnects abstract the interconnect details and provide predictability in the data transfer, which are desirable not only for the functional domain but also for the test application. The proposed wrapper is implemented in VHDL and integrated to the Ethereal NoC. The results show the impact of bandwidth in the core test time. The wrapper area and core test time are compared with a wrapper design for dedicated TAM

Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets

An automatic test pattern generation (ATPG) procedure for linear analog circuits is presented in this work. A fault-based multifrequency test approach is considered. The procedure selects a minimal set of test measures and generates the minimal set of frequency tests which guarantee maximum fault coverage and, if required, maximal fault diagnosis, of circuit AC hard/soft faults. The procedure is most suitable for linear time-invariant circuits which present significant frequency-dependent fault effects.For test generation, the approach is applicable once parametric tests have determined DC behaviour. The advantage of this procedure with respect to previous works is that it guarantees a minimal size test set. For fault diagnosis, a fault dictionary containing a signature of the effects of each fault in the frequency domain is used. Fault location and fault identification can be achieved without the need of analog test points, and just in-circuit checkers with an observable go/no-go digital output are required for diagnosis.The procedure is exemplified for the case of an analog biquadratic filter. Three different self-test approaches for this circuit are considered. For each self-test strategy, a set of several test measures is possible. The procedure selects, in each case, the minimal set of test measures and the minimal set of frequency tests which guarantee maximum fault coverage and maximal diagnosis. With this, the self-test approaches are compared in terms of the fault coverage and the fault diagnosability achieved.

A reliable fail-safe system

The paper describes a fault tolerant system that is based on two replicas of a self checking module and on an error masking interface. The main contributions of this work rely on the fail safe/strongly fail safe design of the error masking interface, and on the analysis of the competitiveness of this fault tolerant scheme with respect to its reliability.

Designing self-exercising analogue checkers

The design of checkers suitable for concurrent error detection in analogue and mixed-signal circuits is addressed in this paper. These checkers can on-line test duplicated and fully differential analogue functional circuits and comply with existing digital self-checking parts. A test pattern generator for off-line testing of the checkers is proposed, which fully exercises their capability of signalling functional error occurrences.<<ETX>>

Improving yield of torus nocs through fault-diagnosis-and-repair of interconnect faults

We propose a fault tolerance method for torus NoCs capable of increase the yield with minimal performance overhead. The proposed approach consists in detecting and diagnosing interconnect faults using BIST structures and activating alternative paths for the faulty links. Experimental results show that alternative fault-free paths are found by the dynamic routing for 95% of the diagnosed faults (stuck-at and pairwise shorts within a single link or between any two links).

Analog checkers with absolute and relative tolerances

The design of checkers aimed at the concurrent test of analog and mixed-signal circuits is considered in this paper. These checkers can on-line test duplicated and fully differential analog circuits. The test approach is based on exploiting the inherent redundancy of these circuits which results in the use of a code for the analog signals. The analog code is monitored by the checkers. An error signal which complies with existing digital self-checking parts is generated in the case that a code fails out of the valid code space. For the verification of the analog codes, absolute tolerance margins and tolerance margins which are made relative to signal amplitude are considered. A test pattern generator for off-line testing of the checkers is proposed. >

FAULT SIMULATION OF MEMS USING HDLS

This paper describes an approach to fault simulation of MEMS using an analog Hardware Description Language (HDL). HDL languages facilitate the description of mixed-domain devices, providing powerful representation capabilities which are not limited to the use of the traditional equivalent electrical modes. This is exploited in this paper for fault simulation of MEMS, showing the advantages of using an HDL for this task. An electro-thermal converter is used as test vehicle, for which an equivalent electrical more is readily obtained. Typical defects and failure mechanisms which can affect these devices fabricated using CMOS-compatible bulk micromachining are shown. These defects are used for illustrating the fault simulation approach which appears to be more comprehensive and systematic than previous approaches.