Alireza Rohani

Rapid transient fault insertion in large digital systems

This paper presents a technique for rapid transient fault injection, regarding the CPU time, to perform simulation-based fault-injection in complex System-on-Chip Systems (SoCs). The proposed approach can be applied to complex circuits, as it is not required to modify the top-level modules of a design; moreover, it is capable to inject a wide range of fault models in a design and finally a competitive reduction in terms of CPU time will be achieved. The root of our method is based on the usage of simulator-commands along with partial code modification techniques. To prove the efficiency of the proposed method, it has been implemented on two case studies, a pre-synthesized netlist of an AVR microcontroller from ATMEL and a post placed-and-routed Verilog netlist of a high performance reconfigurable processor in 90-nm UMC technology, Xentium processor from Recore Systems. Experimental results show that our technique is able to reduce the CPU time by a factor ranging from 27% to 67% compared with typical simulation-based fault-injection approaches and by a factor of 10% compared with rapid simulation-based techniques.

A Technique for Accelerating Injection of Transient Faults in Complex SoCs

This paper presents a technique for reducing CPU time to perform simulation-based fault-injection experiments in complex SoCs. This technique is fully compatible with commercial HDL simulators with no requirement to develop dedicated compilers. This approach can be easily applied to complex SoC models, as it is not required to modify the top-level modules of design, moreover, it can inject a wide range of fault models in the design and finally it can achieve a competitive reduction in terms of CPU time compared with other time-accelerated simulation-based approaches. These goals are achieved by using simulator-commands along with partial code modification techniques. The experimental results show that the proposed technique is able to reduce the CPU time by a factor ranging from 27% to 67% compared with typical simulation-based fault-injection approaches and by a factor of 10% compared with time-accelerating simulation-based techniques.

Thermal issues in test: An overview of the significant aspects and industrial practice

Thermal phenomena occurring along test execution at the final stages of the manufacturing flow are considered as a significant issue for several reasons, including dramatic effects like circuit damage that is leading to yield loss. This paper tries to redeem those bad guys in order to exploit them to improve the test quality, reducing the overall test cost without affecting the yield.

An on-line soft error mitigation technique for control logic of VLIW processors

The soft error phenomenon is forecast to be a real threat for todays technology of ICs. While implementing error detection and correction codes for regular structural memory arrays have been effectively used to stem the emerging soft error threat, utilizing a low overhead approach for the complex and unstructured control logic of modern processors is still a challenge. This paper presents a low overhead reliability enhancement scheme for the control logic of a Very Large Instruction Word (VLIW) processor. First, a soft error sensitivity analysis has been carried out in order to distinguish the most vulnerable signals inside the control unit. Subsequently, these vulnerable control signals have been classified into either an opcode-dependent or instruction-dependent control signal. The strategy for protecting opcode-dependent control signals utilizes a ROM memory, while instruction-dependent control signals are protected using a RAM memory as a cache to store a history of these control signals along with the Triple Modular Redundancy concept to mask the single transient faults. This technique has been implemented on a high-performance processor, the Xentium processor, in order to validate its degree of fault tolerance and performance overhead as well.

A software framework to calculate local temperatures in CMOS processors

A conventional technique to rise temperature in a processor involves the usage of thermal ovens or infrared techniques to heat up and then measure the temperature of the processor. However, local temperatures of each module cannot be controlled by these techniques. This paper presents a software mechanism to heat-up a processor while the temperature of each modules of the processor can precisely be calculated. In order to develop our mechanism, first a mathematical model to correlate dynamic power and local temperature has been developed; next a framework that calculates local temperature for any given workload has been presented. In order to show the details of our model, the proposed framework has been applied to a thirty-two bit full-adder. The applicability of our framework has been demonstrated by using a complex DSP (Digital Signal Processor) as the case study. This paper will show that, despite common belief, there is no linear correlation between dynamic power and local temperatures of a chip.

Detecting intermittent resistive faults in digital CMOS circuits

Interconnection reliability threats dependability of highly critical electronic systems. One of most challenging interconnection-induced reliability threats are intermittent resistive faults (IRFs). The occurrence rate of this kind of defects can take e.g. one month, and the duration of defects can be as short as a few nanoseconds. As a result, evoking and detecting these faults is a big challenge. IRFs can cause timing deviations in data paths in digital systems during its operating time. This paper proposes an online digital slack monitor which is able to detect small timing deviations caused by IRFs in digital systems. The simulation results show that the proposed monitor is effective in detecting IRFs.

Study of the effects of SET induced faults on submicron technologies

The progression of shrinking technologies into processes below 100nm has increased the importance of transient faults in digital systems. Fault injection into the HDL model of the system, known as simulation-based fault injection, is being increasingly used in recent years in order to evaluate the behaviour of systems in the presence of transient faults. However, there are still several questions in conducting simulation-based fault injections. For instance, what is the importance of timing information of the netlist with regard to the accuracy of fault injection results? And how does the number of fault injection experiments relate to obtain a realistic behaviour of the processor under test. Finally, what is the dependence of fault injection results on the processors workload? This paper aims to answer these questions, by studying the effects of transient faults on a post placed-and-routed Verilog netlist of a high performance reconfigurable processor in 90-nanometer UMC technology.

Two soft-error mitigation techniques for functional units of DSP processors

This paper presents two soft-error mitigation methods for DSP processors. Considering that a DSP processor is composed of several functional units and each functional unit constitutes of a control unit, some registers and combinational logic, a unique characteristic of DSP workloads has been deployed to develop a masking mechanism for the control-logic of each functional unit. Combinational logic has been elaborated with a fast recovery mechanism to isolate the fault-free functional units and re-execute the erroneous instruction. These techniques have been implemented on a DSP processor in order to assess the achieved fault-tolerance versus the imposed overheads.

Pulse-length determination techniques in the rectangular single event transient fault model

One of the well-known models to represent Single Event Transient phenomenon at the logic-level is the rectangular pulse model. However, the pulse-length in this model has a vital contribution to the accuracy and validity of the rectangular pulse model. The work presented in this paper develops two approaches for determination of the pulse-length of the rectangular pulse model used in Single Event Transient (SET) faults. The first determination approach has been extracted from radiation testing along with transistor-level SET analysis tools. The second determination approach has been elicited from asymptotic analytical behaviour of SETs in 45-nm CMOS process. The results show that applying these two pulse-length determination approaches to the rectangular pulse model will cause the fault injection results converge much faster (up to sixteen times), compared to other conventional approaches.

On the maximization of the sustained switching activity in a processor

Recently, several application areas in the test domain (e.g., burn-in and aging monitoring) started to require suitable input stimuli, able to maximize the switching activity of a certain module for a certain period of time. If the module is part of a processor, this turns into identifying a suitable sequence of instructions, able to maximize the switching activity. This paper proposes a method to attack this problem, and reports some experimental results gathered on a MIPS-like pipelined processor.