Laurent Demeûs
Université catholique de Louvain
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Publication
Featured researches published by Laurent Demeûs.
Solid-state Electronics | 2001
Denis Flandre; Stéphane Adriaensen; A. Akheyar; André Crahay; Laurent Demeûs; Pierre Delatte; Vincent Dessard; Benjamin Iniguez; Amaury Nève; Bohdan Katschmarskyj; Pierre Loumaye; Jean Laconte; I. Martinez; Gonzalo Picun; E. Rauly; David Spote; Miloud Zitout; Morin Dehan; Bertrand Parvais; Pascal Simon; Danielle Vanhoenacker-Janvier; Jean-Pierre Raskin
Based on an extensive review of research results on the material, process, device and circuit properties of thin-film fully depleted SOI CMOS, our work demonstrates that such a process with channel lengths of about 1 mum may emerge as a most promising and mature contender for integrated microsystems which must operate under low-voltage low-power conditions, at microwave frequencies and/or in the temperature range 200-350 degreesC
IEEE Transactions on Industrial Electronics | 2001
Laurent Demeûs; Vincent Dessard; A. Viviani; Stéphane Adriaensen; Denis Flandre
The electrical characteristics of devices and circuits realized in CMOS technology on silicon-on-insulator (SOI) substrates and operated at elevated temperatures are presented and compared with results obtained using other materials (bulk Si, GaAs, SiC). It is demonstrated that fully depleted CMOS on SOI is the most suitable process for the realization of complex electronic circuits to be operated in high-temperature environments, up to more than 300/spl deg/C.
european solid-state circuits conference | 2005
Pierre Delatte; Gonzalo Picun; Laurent Demeûs; Pascal Simon; Denis Flandre
This paper discusses the power saving of an LC-VCO designed on high-resistivity SOI substrates (/spl rho/ > 1000/spl Omega//spl middot/cm). It demonstrates the drastic improvement in the varactors and inductors quality factor on these substrates. It stresses on the importance of optimizing the tank inductor and the VCO for high-resistivity substrates. A 5GHz VCO designed in a 0.13/spl mu/m partially depleted SOI CMOS confirms the low-power performance with a figure-of-merit greater than 190, placing this design at the top of the state-of-the-art.
ieee sensors | 2002
Denis Flandre; Stéphane Adriaensen; Aryan Afzalian; Jean Laconte; David Levacq; Laurent Vancaillie; Jean-Pierre Raskin; Laurent Demeûs; Pierre Delatte; Vincent Dessard; Gonzalo Picun
In this paper, we demonstrate how a simple fully-depleted SOI CMOS process can be adapted to provide a wide range of performance compatible with the realization of heterogeneous micropower, high-temperature or RF micro-systems which involve the integration of sensing, analog and digital components. High-temperature and low-voltage examples are discussed.
european solid-state circuits conference | 1998
Denis Flandre; Laurent Demeûs; Vincent Dessard; A. Viviani; B. Gentinne; Jean-Paul Eggermont
Special techniques are presented for the design of SOI CMOS OTAs which have to operate from room up to very high ambient temperatures. The results of several implementations are reported including applications such as in bandgap and current references as well as Σ-Δ modulators with efficient switch design at elevated temperatures.
SPIE's First International Symposium on Fluctuations and Noise | 2003
Youcef Haddab; Vincent Mosser; Mélanie Lysowec; Jan Suski; Laurent Demeûs; Stéphane Adriaensen; Denis Flandre
Hall sensors are used in a very wide range of applications. A very demanding one is electrical current measurement for metering purposes. In addition to high precision and stability, a sufficiently low noise level is required. Cost reduction through sensor integration with low-voltage/low-power electronics is also desirable. The purpose of this work is to investigate the possible use of SOI (Silicon On Insulator) technology for this integration. We have fabricated SOI Hall devices exploring a wide range of silicon layer thickness and doping level. We show that noise is influenced by the presence of LOCOS and p-n depletion zones near the edges of the active zones of the devices. A proper choice of SOI technological parameters and process flow leads to up to 18 dB reduction in Hall sensor noise level. This result can be extended to many categories of devices fabricated using SOI technology.
IEEE Transactions on Electron Devices | 2001
B. Infguez; Jean-Pierre Raskin; Laurent Demeûs; Amaury Nève; D. Vanhoenacker; Pascal Simon; Michael Goffioul; Denis Flandre
We present a submicrometer RF fully depleted SOI MOSFET macro-model based on a complete extrinsic small-signal equivalent circuit and an improved CAD model for the intrinsic device. The delay propagation effects in the channel are modeled by splitting the intrinsic transistor into a series of shorter transistors, for each of which a quasistatic device model can be used. Since the intrinsic device model is charge-based, our RF SOI MOSFET model can be used in both small and large-signal analyses. The model has been validated for frequencies up to 40 GHz and effective channel lengths down to 0.16 /spl mu/m.
1998 Fourth International High Temperature Electronics Conference. HITEC (Cat. No.98EX145) | 1998
Laurent Demeûs; A. Viviani; Denis Flandre
The feasibility of single chip solutions fully integrating complete analog instrumentation system using thin-film fully-depleted SOI CMOS technology is demonstrated. The performance of our instrumentation amplifiers, continuous-time filters and sigma-delta modulators are compatible with actual specifications from oil drilling or aerospace applications and correct operation is extended up to more than 300/spl deg/C.
international symposium on signals systems and electronics | 1998
Laurent Demeûs; J. Chen; Jean-Paul Eggermont; R. Gillon; Jean-Pierre Raskin; D. Vanhoenacker; Denis Flandre
Thin film fully depleted silicon-on-insulator CMOS technology, devices and circuits for RF applications are presented. These submicron MOSFET transistors can achieve a maximum oscillation frequency of 30 GHz for a 1 V power supply. This kind of performance and the advantages of the SOI transistors fit the needs for low-voltage low-power RF applications. To demonstrate the capabilities of this technology we present a single stage OTA with a f/sub T/ of 1.1 GHz and /spl phi//sub M/ of 30/spl deg/, and two CMOS mixers with exceptional linearity results.
international soi conference | 1997
Laurent Demeûs; Denis Flandre
Summary form only given. The analog MOS switch is one of the major building blocks in switched-data circuits (switched capacitor, current-copier, track-and-hold, etc.). Their main limitation regarding accuracy is linked to the problem of charge injection that induces output voltage errors. Several physical studies recently addressed the charge injection problem in bulk MOSFETs under low-voltage conditions (considering the weak inversion contribution) or in SOI MOSFETs under large voltage transients. In this paper we compare charge injection in bulk and SOI MOS switches from a low-voltage circuit point of view, using MEDICI 2-D simulations, for three different MOS processes: typical bulk with a threshold voltage (VT) of 0.72 V, comparable fully-depleted SOI with VT=0.74 V, and low-voltage SOI. Our analysis has demonstrated significant differences in the charge components injected by bulk and SOI MOS switches and their dependence on process and circuit conditions. In carefully optimized circuits, low-voltage fully depleted SOI MOS switches may inject much less charges than in bulk and enable better compensation results.