Amir N. Hanna

InAs/Si Hetero-Junction Nanotube Tunnel Transistors

Hetero-structure tunnel junctions in non-planar gate-all-around nanowire (GAA NW) tunnel FETs (TFETs) have shown significant enhancement in ‘ON’ state tunnel current over their all-silicon counterpart. Here we show the unique concept of nanotube TFET in a hetero-structure configuration that is capable of much higher drive current as opposed to that of GAA NW TFETs.Through the use of inner/outer core-shell gates, a single III-V hetero-structured nanotube TFET leverages physically larger tunneling area while achieving higher driver current (ION) and saving real estates by eliminating arraying requirement. Numerical simulations has shown that a 10 nm thin nanotube TFET with a 100 nm core gate has a 5×normalized output current compared to a 10 nm diameter GAA NW TFET.

Zinc oxide integrated area efficient high output low power wavy channel thin film transistor

We report an atomic layer deposition based zinc oxide channel material integrated thin film transistor using wavy channel architecture allowing expansion of the transistor width in the vertical direction using the fin type features. The experimental devices show area efficiency, higher normalized output current, and relatively lower power consumption compared to the planar architecture. This performance gain is attributed to the increased device width and an enhanced applied electric field due to the architecture when compared to a back gated planar device with the same process conditions.

Si/Ge hetero-structure nanotube tunnel field effect transistor

We discuss the physics of conventional channel material (silicon/germanium hetero-structure) based transistor topology mainly core/shell (inner/outer) gated nanotube vs. gate-all-around nanowire architecture for tunnel field effect transistor application. We show that nanotube topology can result in higher performance through higher normalized current when compared to nanowire architecture at Vdd = 1 V due to the availability of larger tunneling cross section and lower Shockley-Reed-Hall recombination. Both architectures are able to achieve sub 60 mV/dec performance for more than five orders of magnitude of drain current. This enables the nanotube configuration achieving performance same as the nanowire architecture even when Vdd is scaled down to 0.5 V.

Area and Energy Efficient High-Performance ZnO Wavy Channel Thin-Film Transistor

Increased output current while maintaining low power consumption in thin-film transistors (TFTs) is essential for future generation large-area high-resolution displays. Here, we show wavy channel (WC) architecture in TFT that allows the expansion of the transistor width in the direction perpendicular to the substrate through integrating continuous fin features on the underlying substrate. This architecture enables expanding the TFT width without consuming any additional chip area, thus enabling increased performance while maintaining the real estate integrity. The experimental WCTFTs show a linear increase in output current as a function of number of fins per device resulting in 3.5× increase in output current when compared with planar counterparts that consume the same chip area. The new architecture also allows tuning the threshold voltage as a function of the number of fin features included in the device, as threshold voltage linearly decreased from 6.8 V for planar device to 2.6 V for WC devices with 32 fins. This makes the new architecture more power efficient as lower operation voltages could be used for WC devices compared with planar counterparts. It was also found that field effect mobility linearly increases with the number of fins included in the device, showing almost 1.8× enhancements in the field effect mobility than that of the planar counterparts. This can be attributed to higher electric field in the channel due to the fin architecture and threshold voltage shift.

CMOS compatible fabrication of flexible and semi-transparent FeRAM on ultra-thin bulk monocrystalline silicon (100) fabric

Commercialization of flexible electronics requires reliable, high performance, ultra-compact and low power devices. To achieve them, we fabricate traditional electronics on bulk mono-crystalline silicon (100) and transform the top portion into an ultra-thin flexible silicon fabric with pre-fabricated devices, preserving ultra-large-scale-integration density and same device performance. This can be done in a cost effective manner due to its full compatibility with standard CMOS processes. In this paper, using the same approach, for the first time we demonstrate a ferroelectric random access memory (FeRAM) cell on flexible silicon fabric platform and assess its functionality and practical potential.

Vertical bifacial solar farms: Physics, design, and global optimization

There have been sustained interest in bifacial solar cell technology since 1980s, with prospects of 30–50% increase in the output power from a stand-alone panel. Moreover, a vertical bifacial panel reduces dust accumulation and provides two output peaks during the day, with the second peak aligned to the peak electricity demand. Recent commercialization and anticipated growth of bifacial panel market have encouraged a closer scrutiny of the integrated power-output and economic viability of bifacial solar farms, where mutual shading will erode some of the anticipated energy gain associated with an isolated, single panel. Towards that goal, in this paper we focus on geography-specific optimization of ground-mounted vertical bifacial solar farms for the entire world. For local irradiance, we combine the measured meteorological data with the clear-sky model. In addition, we consider the effects of direct, diffuse, and albedo light. We assume the panel is configured into sub-strings with bypass-diodes. Based on calculated light collection and panel output, we analyze the optimum farm design for maximum yearly output at any given location in the world. Our results predict that, regardless of the geographical location, a vertical bifacial farm will yield 10–20% more energy than a traditional monofacial farm for a practical row-spacing of 2m (corresponding to 1.2m high panels). With the prospect of additional 5–20% energy gain from reduced soiling and tilt optimization, bifacial solar farm do offer a viable technology option for large-scale solar energy generation.

Zinc Oxide Integrated Wavy Channel Thin-Film Transistor-Based High-Performance Digital Circuits

High-performance thin film transistor (TFT) can be a great driving force for display, sensor/actuator, integrated electronics, and distributed computation for the Internet of Everything applications. While semiconducting oxides, such as zinc oxide (ZnO), present promising opportunity in that regard, still wide area of improvement exists to increase the performance further. Here, we show a wavy channel (WC) architecture for ZnO integrated TFT, which increases transistor width without chip area penalty, enabling high performance in material agnostic way. We further demonstrate digital logic NAND circuit using the WC architecture and compare it with the conventional planar architecture. The WC architecture circuits have shown 2× higher peak-to-peak output voltage for the same input voltage. They also have 3× lower high-to-low propagation delay times, respectively, when compared with the planar architecture. The performance enhancement is attributed to both extra device width and enhanced field-effect mobility due to higher gate field electrostatics control.

Water soluble nano-scale transient material germanium oxide for zero toxic waste based environmentally benign nano-manufacturing

In the recent past, with the advent of transient electronics for mostly implantable and secured electronic applications, the whole field effect transistor structure has been dissolved in a variety of chemicals. Here, we show simple water soluble nano-scale (sub-10 nm) germanium oxide (GeO2) as the dissolvable component to remove the functional structures of metal oxide semiconductor devices and then reuse the expensive germanium substrate again for functional device fabrication. This way, in addition to transiency, we also show an environmentally friendly manufacturing process for a complementary metal oxide semiconductor (CMOS) technology. Every year, trillions of complementary metal oxide semiconductor (CMOS) electronics are manufactured and billions are disposed, which extend the harmful impact to our environment. Therefore, this is a key study to show a pragmatic approach for water soluble high performance electronics for environmentally friendly manufacturing and bioresorbable electronic applications.

Wavy Channel architecture thin film transistor (TFT) using amorphous zinc oxide for high-performance and low-power semiconductor circuits

We report a Wavy Channel (WC) architecture thin film transistor (TFT) for extended device width by integrating continuous vertical fin like features with lateral continuous plane in the substrate. For a WC TFT which has 50% larger device width, the enhancement in the output drive current is 100%, when compared to a conventional planar TFT consuming the same chip area. This current increase is attributed to both the extra width and enhanced field effect mobility due to corner effects. This shows the potential of WC architecture to boast circuit performance without the need for aggressive gate length scaling.

Wavy Channel TFT-Based Digital Circuits

We report a wavy channel (WC) architecture thin-film transistor-based digital circuitry using ZnO as a channel material. The novel architecture allows for extending device width by integrating vertical finlike substrate corrugations giving rise to 50% larger device width, without occupying extra chip area. The enhancement in the output drive current is 100%, when compared with conventional planar architecture for devices occupying the same chip area. The current increase is attributed to both the extra device width and 50% enhancement in field-effect mobility due to electrostatic gating effects. Fabricated inverters show that WC inverters can achieve two times the peak-to-peak output voltage for the same input when compared with planar devices. In addition, WC inverters show 30% faster rise and fall times, and can operate up to around two times frequency of the planar inverters for the same peak-to-peak output voltage. WC NOR circuits have shown 70% higher peak-to-peak output voltage, over their planar counterparts, and WC pass transistor logic multiplexer circuit has shown more than five times faster high-to-low propagation delay compared with its planar counterpart at a similar peak-to-peak output voltage.