J.P. de Gyvez

Resistance characterization for weak open defects

Strong open defects can cause a circuit to malfunction, but even weak open defects can cause it to function poorly. Detecting weak opens is thus an important, but challenging, task. Characterizing weak opens can help researchers assess the need for delay fault tests.

On-chip digital power supply control for system-on-chip applications

The authors presented an on-chip, fully-digital, power-supply control system. The scheme consists of two independent control loops that regulate power supply variations due to semiconductor process spread, temperature, and chips workload. Smart power-switches working as linear voltage regulators are used to adjust the local power supply. The smart power-switch allows us to keep the global power network unchanged. It offers an integrated standby mode and has a fast dynamic response, i.e. low transition times between voltage steps at the cost of the reduced power conversion efficiency when compared to complex DC-DC converters.

Testing and diagnosis of power switches in SOCs

The use of power switches in modern system chips (SOCs) is inevitable as they allow for efficient on-chip static power management. Leakage is today one of the main hurdles in low-power applications. Power switches enable power gating functionality, i.e., one or more parts of the SOC can be powered-off during standby mode leading in this way to savings in the overall SOCs power consumption. In this paper, we present a circuit and a method to test power switches. The proposed method allows testing of on/off functionality. In case of segmented power switches individual failing segments can be identified as well by using the proposed test strategy. The method requires only a small number of test patterns that are easy to generate. Furthermore, the proposed method is very scalable with the number of power switches and has a very small area-overhead

Power supply noise monitor for signal integrity faults

We propose a monitor able to detect on-line excessive power supply noise (PSN) at the power/ground lines. It has high resolution (100 ps), enough to collect the important features of PSN and its output is isolated from the local PSN. It is useful for any scheme that takes corrective actions to prevent signal integrity faults after detection of excessive PSN.

Word line pulsing technique for stability fault detection in SRAM cells

Stability testing of SRAMs has been time consuming. This paper presents a new programmable DFT technique for detection of stability and data retention faults in SRAM cells. The proposed technique offers extended flexibility in setting the weak overwrite test stress, which allows to track process changes without time-consuming post-silicon design iterations. Moreover, it does not introduce extra circuitry in the SRAM array and surpasses the data retention test in test time and detection capability

Power-scan chain: design for analog testability

This paper reports a design for testability technique, which provides necessary diagnostic capability for signature-based testing of analog circuits. To facilitate this kind of testing, it is preferable to observe the current (or voltage) signatures of individual cores instead of observing the current (or voltage) signature of the whole analog SoC. Therefore, our DfT works like a power-scan chain aimed at turning on/off analog cores in an individual manner, providing an observability means at the cores power and output terminals, and at exciting the core under test. The proposed DfT can be used for engineering pre-characterization as well, and can easily be interfaced to standards like I2C and IEEE 1149.1 TAP controllers. In this paper, we further provide experimental evidence of our approach as applied to an RF device

Evaluation of signature-based testing of RF/analog circuits

Due to its low cost, low test time and reduced test complexity, structural testing is preferred to functional whenever possible. The study presented in this paper indicates that the two low-frequency structural test methods considered, power supply current monitoring and the power supply ramping technique, provide a valuable supplement/alternative when one of the functional tests (gain, noise figure and total harmonic distortion) in the test set can be complemented or substituted by structural test and add to or maintain no loss of fault coverage.

Limits to performance spread tuning using adaptive voltage and body biasing

We examine technology constraints on tuning active power and delay using adaptive voltage scaling (AVS) and adaptive body biasing (ABB) design techniques. To serve this purpose, a test circuit was fabricated in a 90 nm triple-well low-power CMOS technology. The presented analysis is based on a ring oscillator running at 488 MHz and a circular shift register with 8 K flip-flops and 50 K gates. Measurement results indicate that it is possible to reach 24.4/spl times/ power savings by 6.1/spl times/ frequency downscaling using AVS, /spl plusmn/24% power and /spl plusmn/22% frequency tuning at nominal conditions using ABB only, 127/spl times/ power savings with 37.4/spl times/ frequency downscaling by combining AVS and ABB.

Average leakage current estimation of CMOS logic circuits

In a product engineering environment there is a need to know quickly the average standby current of an IC for various combinations of power supply and temperature. We present two techniques to do this estimation without resorting to involved simulations. We use a bottom-up methodology that propagates the effect of process variations to higher levels of abstraction. In one approach, the leakage current of any given circuit is computed by adding up individual cell currents indexed from a statistically characterized library of standard cells. The second method is based on empirical formulae derived from results of the standard cell library characterization. In this approach the total leakage current is estimated without the need for any simulations and using only the circuits equivalent cell-count. We present here the statistical foundation of our approach as well as experimental results on actual ICs.

Programmable techniques for cell stability test and debug in embedded SRAMs

Reliable cell stability test of modern embedded SRAMs calls for DFT techniques with a flexible detection threshold. We present two programmable cell stability test and debug techniques that use partially discharged floating bit lines to apply a weak overwrite stress to a cell under test. The applied stress can be digitally adjusted to track the process variations or the desired pass/fail threshold. The proposed techniques are demonstrated to exceed the regular data retention test in both the defect coverage and detection range