Subho Chatterjee

An energy efficient cache design using spin torque transfer (STT) RAM

The on-chip memory is a dominant source of power and energy consumption in modern and future processors. This paper explores the use of a new emerging non-volatile memory technology as a replacement for SRAM based lower level caches — Spin Torque Transfer(STT) RAM. While STTRAM achieves a reduction in leakage energy of 90% compared to SRAM, the dynamic energy for a write operation is 2X that of SRAM. Consequently, we propose additional microarchitectural optimizations to reduce overall dynamic energy which achieve an average reduction in dynamic energy over the base case of 30% with a range of 16% to 60% across 10 benchmarks.

A Scalable Design Methodology for Energy Minimization of STTRAM: A Circuit and Architecture Perspective

In this paper, we analyze the energy dissipation in spin-torque-transfer random access memory array (STTRAM). We present a methodology for exploring the design space to minimize the energy dissipation of the array while maintaining required read and write quality for a given magnetic tunnel junction technology. The proposed method shows the need for proper choice of the silicon transistor width and array operating voltage to minimize the energy dissipation of the STTRAM array. The write energy is found to be 10 × greater than read energy. Hence, read-write ratio becomes a crucial factor that determines energy for STTRAM last level caches (L2). An exploration is performed across several architectural benchmarks including shared and non-shared caches for detailed energy analysis.

Energy-Efficient Reconfigurable Computing Using a Circuit-Architecture-Software Co-Design Approach

Reconfigurable computing frameworks such as field programmable gate array (FPGA) provide flexibility to map arbitrary applications. However, their intrinsic flexibility comes at the cost of significantly worse performance and power dissipation than their custom counterparts. Existing design solutions such as voltage scaling and multi-threshold assignment typically trade off energy for performance or vise versa. In this paper, we show that an integrated circuit-architecture-software co-design approach can be extremely effective to simultaneously improve the power and performance of a reconfigurable hardware framework, leading to large improvement in energy-delay product (EDP). First, we select a spatio-temporal reconfigurable computing architecture based on 2-threshold assignment-D memory-array. Applications are mapped to memory as multiple-input multiple-output lookup tables (LUTs) and are evaluated in temporal manner inside a computing element. Multiple such computing elements communicate spatially through programmable interconnects. Next, we exploit the read-dominant memory access pattern in reconfigurable hardware to design an asymmetric memory cell, which provides higher read performance and lower read power leading to improvement in the overall EDP during operation. We note that the proposed memory cell is also asymmetric in terms of its content, providing better read power for one of the logic states (logic “0” or “1”). Based on this observation, next we propose a content-aware application mapping approach, which tries to maximize the logic “0” or logic “1” content in the lookup tables. A design flow is presented to incorporate the proposed architecture, asymmetric memory cell design and content-aware mapping. We show that for both nanoscale complementary metal-oxide-semiconductor (CMOS) [static random access memory (SRAM)] as well as emerging non-CMOS [spin torque transfer random access memory (STTRAM)] memory technologies, such a co-design solution can achieve significant improvement in system EDP over a conventional FPGA framework.

Exploring Spin Transfer Torque Devices for Unconventional Computing

This paper reviews the potential of spin-transfer torque devices as an alternative to complementary metal-oxide-semiconductor for non-von Neumann and non-Boolean computing. Recent experiments on spin-transfer torque devices have demonstrated high-speed magnetization switching of nanoscale magnets with small current densities. Coupled with other properties, such as nonvolatility, zero leakage current, high integration density, we discuss that the spin-transfer torque devices can be inherently suitable for some unconventional computing models for information processing. We review several spintronic devices in which magnetization can be manipulated by current induced spin transfer torque and explore their applications in neuromorphic computing and reconfigurable memory-based computing.

A methodology for robust, energy efficient design of Spin-Torque-Transfer RAM arrays at scaled technologies

In this paper we propose a methodology for energy efficient Spin-Torque-Transfer Random Access Memory (STTRAM) array design at scaled technology nodes. We present a model to estimate and analyze the energy dissipation of an STTRAM array. The presented model shows the strong dependence of the array energy on the silicon transistor width, word line voltage and row/column organization. Using the array energy model we propose a design methodology for STTRAM arrays which minimizes the energy dissipation while maintaining the required robustness in read and write operations at scaled technologies.

Impact of die-to-die thermal coupling on the electrical characteristics of 3D stacked SRAM cache

We study the thermal coupling in a 3D stack with multiple cores in one tier and an SRAM array (cache) in a second tier with face-to-back bonding. For identical statistical distribution of power dissipation in cores, the SRAM sub-arrays experience much higher mean and variance in temperature in a 3D stack compared to a conventional 2D system. The increased variability in temperature increases leakage, degrades performance, and accelerates aging in 3D integrated SRAM. This is studied using 32nm predictive technology. Further, the spatial and temporal variations in performance of SRAM blocks become a strong function of the power variations in cores.

A Memory-Based Logic Block With Optimized-for-Read SRAM for Energy-Efficient Reconfigurable Computing Fabric

A memory-based logic block (MLB), which is a building block for memory-based reconfigurable computing framework, is presented in 130-nm CMOS. The MLB is designed with an optimized-for-read (OFR) 6T static random access memory (SRAM)-based lookup table and demonstrates single- and multicycle evaluation of complex functions. Power-aware mapping leverages the data-dependent read power of the OFR SRAM to reduce MLB evaluation power.

Magneto-resistive property study of direct and indirect band gap thermoelectric Bi-Sb alloys

We report magneto-resistive properties of direct and indirect band gap Bismuth-Antimony (Bi-Sb) alloys. Band gap increases with magnetic field. Large positive magnetoresistance (MR) approaching to 400% is observed. Low field MR experiences quadratic growth and at high field it follows a nearly linear behavior without sign of saturation. Carrier mobility extracted from low field MR data depicts remarkable high value of around 5 m2V−1s−1. Correlation between MR and mobility is revealed. We demonstrate that the strong nearly linear MR at high field can be well understood by classical method, co-build by Parish and Littlewood, Nature 426, 162 (2003) and Phys. Rev. B 72, 094417 (2005).

Impact of Self-Heating on Reliability of a Spin-Torque-Transfer RAM Cell

This paper estimates the temperature distribution within a spin-torque-transfer RAM (STTRAM) cell due to self-heating using a thermal simulation based on the finite volume method. The analysis shows that, due to high switching current and small volume of the magnetic tunnel junction (MTJ), there can be significant rise in temperature in the MTJ as well as the silicon transistor. The impacts of the increased temperature on operational reliability metrics of the STTRAM cell, i.e., read disturb, write failure, and sensing accuracy, are evaluated. It is shown that, due to the self-heating effect, the operational reliability of an STTRAM cell depends on the read-write history of that cell.

Power Aware Post-manufacture Tuning of Analog Nanocircuits

Process variations play a critical role in determining performance of scaled CMOS and other non-CMOS nanodevices. In this paper a power conscious post manufacture tuning technique is proposed for robust analog circuit fabrication with nanodevices in the presence of process variations. The response of the circuit to an optimized test signal is captured and using regression models, the proposed algorithm finds the best setting of tuning knobs for which the shifts in specifications from their nominal values are minimized in a power-aware manner. To demonstrate the proposed algorithm, a two stage Miller compensated operational amplifier is designed using carbon nanotube field effect transistors (CNFETs) and variability effects due to metallic CNT growth, diameter and chirality variations on the performance of the underlying circuits are studied. Suitable tuning knobs for the CNFET op-amp are identified based on the specifications to be tuned. Simulation results show that the proposed tuning algorithm enables overall yield improvement of 25.38% while minimizing power consumption of the tuned devices.