Wen Yueh

Improving IC Security Against Trojan Attacks Through Integration of Security Monitors

This paper describes using on-chip monitors to significantly improve the sensitivity of side-channel signal analysis techniques to malicious inclusions in integrated circuits known as hardware Trojans.

Role of power grid in side channel attack and power-grid-aware secure design

Side-channel attack (SCA) is a method in which an attacker aims at extracting secret information from crypto chips by analyzing physical parameters (e.g. power). SCA has emerged as a serious threat to many mathematically unbreakable cryptography systems. From an attackers point of view, the difficulty of mounting SCA largely depends on Signal-to-Noise Ratio (SNR) of the side-channel information. It has been shown that SNR primarily depends on algorithmic and circuit-level implementation, measurement noise, as well as device thermal noise. However, to the best of our knowledge, there has not been any study on the effect of power delivery network (PDN) on SCA resistance. We note that the PDN plays a significant role in SNR of measured supply current. Furthermore, SCA resistance strongly depends on the operating frequency due to RLC structure of a power grid. In this paper, we analyze the effect of power grid on SCA and provide quantitative results to demonstrate the frequency-dependent SCA resistance due to PDN-induced noise. This property can potentially be exploited by an attacker to facilitate the attack by operating a device at favorable frequency points. On the other hand, from a designers perspective, one can explore countermeasures to secure the device at all operating frequencies while minimizing the design overhead. Based on this observation, we propose a frequency-dependent noise-injection based compensation technique to efficiently protect against SCA. Simulation results using realistic PDN model as well as experimental measurements using FPGA test board validate the observations on role of PDN in SCA and the efficacy of the proposed compensation approach.

Enhancement in CMOS chip performance through microfluidic cooling

High on-chip temperature can degrade chip performance, and increase high leakage power which contributes to a significant part of the total chip power consumption. Microfluidic cooling is believed to have better cooling ability than air cooling. However, very few experimental demonstrations of CMOS chips with integrated microfluidic cooling exist. This paper presents experimental results of a working CMOS chip capable of generating controllable heat and on-chip temperature sensing under air cooling and microfluidic cooling. Under natural air cooling, the leakage current increases exponentially by 1.9 X as the temperature increases from 26.3 °C to 57.6 °C. 18.8 °C temperature drop and 66.2% leakage current saving is achieved by microfluidic cooling compared to natural air cooling at heatflux 34.5 W/cm2. In addition, the time to reach a steady state in response to a sudden application of microfluidic cooling is only 48.5% of that of forced air cooling. Lastly, increasing the flow rate of microfluidic cooling does not decrease the temperature and leakage current much.

Impact of Through-Silicon-Via capacitance on high frequency supply noise in 3D-stacks

We analyze the bias and frequency dependent capacitance of the Power/Ground (P/G) Through-Silicon-Via (TSVs) and its impact on the high-frequency noise in the power delivery network (PDN) of a 3D stack. We show that the P/G TSVs in a 3D PDN act as on-chip distributed decoupling capacitances and hence, help reduce the high-frequency impedance. We present that for the same cross-sectional area, P/G TSVs created using a cluster of small diameter TSVs has higher capacitance than a single large diameter TSV and hence, can further reduce the high-frequency PDN impedance.

A Memory-Based Logic Block With Optimized-for-Read SRAM for Energy-Efficient Reconfigurable Computing Fabric

A memory-based logic block (MLB), which is a building block for memory-based reconfigurable computing framework, is presented in 130-nm CMOS. The MLB is designed with an optimized-for-read (OFR) 6T static random access memory (SRAM)-based lookup table and demonstrates single- and multicycle evaluation of complex functions. Power-aware mapping leverages the data-dependent read power of the OFR SRAM to reduce MLB evaluation power.

Field programmable thermal emulator (FPTE): An all-silicon test structure for thermal characterization of integrated circuits

This paper presents an on-chip digitally programmable test structure, referred to as the field programmable thermal emulator (FPTE), for on-line characterization of power pattern, time-varying thermal field, and associated changes in the electrical characteristics of the transistors. A test chip was designed in 130nm CMOS to validate the test structure. The measurement results demonstrated the ability of FPTE to emulate various power patterns and capture the effects on temperature and circuit performance.

Post-Silicon Estimation of Spatiotemporal Temperature Variations Using MIMO Thermal Filters

This paper experimentally demonstrates a methodology for proactive estimation of spatiotemporal variations in junction temperature of a silicon chip using multi-input multi-output (MIMO) thermal filters. The presented approach performs on-chip measurements to estimate the relations between power and temperature variations in the frequency domain to construct a MIMO thermal filter. The extracted filter is then used to predict spatiotemporal temperature variations from a known power pattern, even for locations without temperature sensors. The accuracy of the proposed approach is verified through a thermal emulator designed in 130-nm CMOS technology with on-chip digitally controllable power (heat) generators and temperature sensors. Using the proposed MIMO thermal filter, spatiotemporal temperature variations are accurately estimated with small error bound even at locations with no temperature sensors.

In Situ Power Gating Efficiency Learner for Fine-Grained Self-Adaptive Power Gating

A low-power in situ learner circuit is presented to characterize the tradeoff between leakage saving and transition energy overhead in power gating (PG). A self-adaptive PG scheme is demonstrated that utilizes the learner circuit to adaptively invoke PG only when leakage saving is more than the transition energy overhead. A 130-nm test chip demonstrates functionality of the learner circuit and its application to adaptive PG under varying process, temperature, and idle signal pattern.

Perceptual quality preserving SRAM architecture for color motion pictures

This work proposes a low power methodology for video framebuffers to preserve the perceptual quality while reducing SRAM power. The bank-wise voltage scaling combined with error masking circuitry is proposed where voltage domains are separated according to the importance of luminous and color channels. The implementation may apply to standard embedded memory cores without redesigning specialized hardware within the SRAM bank. The simulation results showed that the proposed channel protection technique produced better energy-quality trade-off than the conventional higher-order-bit protection for the uncompressed as well as compressed motion image frames.

Performance and Robustness of 3-D Integrated SRAM Considering Tier-to-Tier Thermal and Supply Crosstalk

This paper analyzes the effect of tier-to-tier thermal and supply crosstalk on the performance and robustness of the static random access memory (SRAM) within a 3-D stack under crosstalk influence of the logic cores. Our framework integrates distributed process variation aware circuit analysis, RC-based thermal simulation, and distributed RLC-based power delivery network simulation. The analysis shows when the logic cores and SRAMs are integrated in 3-D stack, the thermal and supply crosstalk degrade the SRAM performance and noise margin during read and write operations.