Amr Amin Hafez

A Blocker-Tolerant, Noise-Cancelling Receiver Suitable for Wideband Wireless Applications

A new wideband receiver architecture is proposed that employs two separate passive-mixer-based downconversion paths, which enables noise cancelling, but avoids voltage gain at blocker frequencies. This approach significantly relaxes the trade-off between noise, out-of-band linearity and wideband operation. The resulting prototype in 40 nm is functional from 80 MHz to 2.7 GHz and achieves a 2 dB noise figure, which only degrades to 4.1 dB in the presence of a 0 dBm blocker.

A blocker-tolerant wideband noise-cancelling receiver with a 2dB noise figure

As narrowband off-chip RF filtering is not compatible with the concept of software-defined radio (SDR), an SDR receiver must be designed to tolerate large out-of-band blockers with minimal gain compression and noise figure degradation. A recent circuit tackles this problem by dispensing with the LNA entirely. This mixer-first approach achieves impressive linearity, but at the expense of noise figure and, since such a receiver has no gain prior to down-conversion, the flicker noise corner can be unacceptably high. Other SDR attempts invariably use a noise-cancelling LNA at the front end, which provides wideband matching, however such approaches have either inadequate linearity or display too large a noise for our purposes. In this work, we propose a hybrid frequency-translational, noise-cancelling (FTNC) receiver that employs two separate down-conversion paths to enable noise cancelling with no voltage gain prior to base-band filtering. The resulting design has a sub-2dB noise figure and tolerates 0dBm blockers with no gain back-off, breaking the traditional noise-linearity trade-off common in all receivers.

A 32-to-48Gb/s serializing transmitter using multiphase sampling in 65nm CMOS

Serial-link transmitters are widely used in applications like optical transceivers and multi-gigabit Ethernet. At tens of Gb/s, the operating range of bit-rates is narrow; limited by the speed of the multiplexing and the setup and hold time constraints of the last stage in the serializer. This constraint leads to using delay-matching buffers [1] or delay calibration loops [1-2] to guarantee that timing constraints are always met at the desired bit-rate across all PVT corners. This additional circuitry increases power, area, and overall complexity of the transmitter. The timing constraint and power penalty are particularly severe when the data rate is high compared to the inherent speed of the technology.

Design and Optimization of Multipath Ring Oscillators

Multipath ring oscillators have been used to generate multiple clock phases and higher oscillation frequencies. This paper presents a modified linear analysis to find an accurate expression for the oscillation frequency and phase noise. The analysis shows that for the same power consumption, the number of phases can be increased without decreasing the oscillation frequency or degrading the phase noise. The expression further indicates factors that determine the oscillation frequency and shows that in principle, the maximum oscillation frequency can exceed that of a three-stage ring oscillator. The analytical results can be used to find the optimum coupling structure of the oscillator to achieve a desired operating frequency and phase noise performance.

A 4.6GHz MDLL with −46dBc reference spur and aperture position tuning

Multiplying delay-locked loops (MDLLs) [1–5] have been shown to have improved jitter accumulation and tracking over VCO-based PLLs. By injecting the reference clock edge into the VCO at each reference cycle, an MDLL removes the accumulated jitter of the VCO. The principal challenge in MDLL design is to align the injected reference edge with the loop feedback signal. Timing mismatch between the reference edge and the VCO feedback edge, or offsets in the charge pump, would introduce a phase error in the injected edge. The error manifests as a period jitter or reference spur in the frequency domain. This effect limits the minimum jitter attained by the MDLL.

A 0.1–1.5 GHz 8-bit Inverter-Based Digital-to-Phase Converter Using Harmonic Rejection

In this paper, a 0.1-1.5 GHz 8-bit inverter-based digital-to-phase converter (DPC) is proposed. Conventional inverter-based DPC suffers from poor linearity and limited output frequency range. To mitigate the linearity problem and extend the output frequency range, we propose to use harmonic rejection (HR) filter to cancel out the 3rd- and 5th-order harmonics of the phase interpolated signal. The residual INL and DNL can be further eliminated by nonlinear interpolation technique. Designed and fabricated in 65-nm CMOS technology, the DPC demonstrates a maximum INL and DNL of 2.18 and 0.89 LSB while consumes a power of 4.3 mW and occupies 0.06 mm2 area.

A 32–48 Gb/s Serializing Transmitter Using Multiphase Serialization in 65 nm CMOS Technology

A power-efficient transmitter is proposed using a multiphase serializer, multiphase dividers using injection-locked oscillators, and a high-speed multiplexing structure to relax the timing constraints. With this architecture, bit times near 1 FO-4 gate delay are achieved using only nominal VT devices in a 65 nm CMOS technology. The divider and serializer operate over a wide range of data rates between 32 and 48 Gb/s limited mainly by the operation range of the frequency synthesizer. The transmitter occupies 0.4 mm2 and consumes 88 mW from a 1.2 V supply which corresponds to 1.8 pJ/bit of power efficiency.

A multi-phase multi-frequency clock generator using superharmonic injection locked multipath ring oscillators as frequency dividers

A phase-locked loop providing multiphase clocks at 12-GHz and its subdivisions is presented. A quadrature VCO with low supply sensitivity is used. Frequency division is achieved using superharmonic injection-locked multipath ring oscillators to extend the maximum division frequency of latch-based dividers without using peaking inductors. A low mismatch charge pump reduces the reference spur level to a worst case of -74 dBc. The phase locked loop is fabricated in 65-nm CMOS. It operates in a frequency band between 7.92-12.14 GHz. The measured phase noise, random jitter, and power consumption at 12.08 GHz output frequency are -127.5 dBc/Hz at 10 MHz offset, 251 fs-rms, and 46.6 mW, respectively.

Analysis and Design of Superharmonic Injection-Locked Multipath Ring Oscillators

Frequency dividers can be modeled as superharmonic injection-locked oscillators. We propose a general model for ring-oscillator based dividers. Theoretically, the maximum division frequency of a frequency divider can be decoupled from the number of phases at its output when multipath coupling of ring oscillators is used. Accurate expressions for the locking range are derived that are used to find the optimum structure to maximize the division frequency. The results of the model are incorporated into a design procedure that can rapidly explore various coupling and sizing of the multipath structure. A design of a divider chain for a 48-Gb/s serializing transmitter is used as a demonstration.

A 0.1-1.5 GHz 8-bit inverter-based digital-to-phase converter using harmonic rejection

This paper presents a digital-to-phase converter (DPC) with 8-bits of resolution and a wide frequency range for the input/output clocks. A harmonic rejection (HR) filter is introduced to improve linearity across a frequency range of 0.1-1.5 GHz. Instead of using time-domain averaging of phase interpolators (PI) in a conventional DPC, the frequency-domain filter directly cancels the 3rd- and 5th-order harmonics of the phase interpolated signal. The architecture is designed using an inverter-based PI circuit structure to improve power consumption and area. The inverter nonlinearity is improved using resistive averaging. The residual INL and DNL are further reduced by nonlinear weighting of the interpolation. Designed and fabricated in 65-nm CMOS technology, the DPC demonstrates a maximum INL and DNL of 1.33 and 0.52 LSB while consumes a power of 4.3 mW and occupies 0.06 mm2 area.