Paul Vande Voorde

MOS C-V characterization of ultrathin gate oxide thickness (1.3-1.8 nm)

An equivalent circuit approach to MOS capacitance-voltage (C-V) modeling of ultrathin gate oxides (1.3-1.8 nm) is proposed. Capacitance simulation including polysilicon depletion is based on quantum mechanical (QM) corrections implemented in a two-dimensional (2-D) device simulator; tunneling current is calculated using a one-dimensional (1-D) Greens function solver. The sharp decrease in capacitance observed for gate oxides below 2.0 nm in both accumulation and inversion is modeled using distributed voltage-controlled RC networks. The imaginary components of small-signal input admittance obtained from AC network analysis agree well with measured capacitance.

Self-Limiting Behavior of Hot Carrier Degradation and Its Implication on the Validity of Lifetime Extraction by Accelerated Stress

The time dependence of hot carrier degradation of n-channel MOSFETs and the methodology of accelerated stress have been investigated in detail. The time (T) dependence is found to be inconsistent with the simple expression of TN (N-0.25), but rather show a slow-down of the degradation rate. The slope of the degradation curve is also found to be dependent on the stress bias voltage. The projection of device lifetime by accelerated stress based on the TN law and the assumption of constant slope independent of stress bias is unreliable.

Accurate doping profile determination using TED/QM models extensible to sub-quarter micron nMOSFETs

Accurate doping profiles are needed to simulate device characteristics. We use capacitance-voltage curves to interrogate the doping profiles, threshold voltage, body effect, poly depletion and oxide thickness on a range of technology generations down to 0.18 /spl mu/m. Proper modeling of both transient enhanced diffusion (TED) and quantum mechanical (QM) effects is essential to ensure the simulations match all aspects of the C-V data. The agreement confirms that the predicted doping profiles are accurate. Device simulations using these doping profiles give the correct threshold voltage, body effect and DIBL characteristics.

Scaling limitations of submicron local oxidation technology

Scaling limitations of LOCOS technology into the submicron regime is explored. Device isolation structures with submicron lines and spaces are fabricated using electron beam lithography. Various LOCOS isolation technologies such as SWAMI, SILO and a new SILO/SWAMI technology are investigated for their scalability to isolation spacing width below one micron based on the requirements of VLSI CMOS technology. It is found that there are two major limitations to the scaling of any LOCOS technology. The first one is the thinning of field oxide with narrower isolation spacing. The second one is the need for a gentle oxidation profile inside silicon for defect free isolation.

C-V and gate tunneling current characterization of ultra-thin gate oxide MOS (t/sub ox/=1.3-1.8 nm)

Direct tunneling of ultra-thin gate oxides results in exponential increases in gate leakage current (Lo et al, 1997). Moreover, the loss of inversion charge due to the carrier quantization then becomes significant. Hence, more physically accurate models are urgently needed. In this paper, an equivalent circuit approach considering the gate tunneling current as well as other QM effects is presented to characterize these phenomena for gate oxide thicknesses ranging from 1.3-1.8 nm.

Density-gradient simulations of quantum effects in ultra-thin-oxide MOS structures

The density-gradient approach to quantum transport theory is used to model the C-V characteristics of MOS devices with ultra-thin gate oxides. The method is shown to provide a physics-based approach the works well in all bias regimes and is simple enough for engineering applications.

Simulation of quantum confinement effects in ultra-thin-oxide MOS structures

The density-gradient approach to quantum transport theory is used to model the inversion layer profiles, threshold voltages and C-V characteristics of MOS capacitors with ultra-thin oxides and polysilicon gates. The results (without fitting parameters) are found to compare quite well with experimental data and with calculations made using quantum mechanics. Comparisons are also made with results obtained using previous phenomenological methods and these favor density-gradient theory as well, especially in its being physically meaningful and predictive. Overall, the results of this work show that density-gradient theory provides a physics-based approach to device modeling problems in which quantum confinement effects are significant that is simple enough for engineering applications.

A method to reduce the peak current density in a via

A new method to alleviate the current crowding problems in the via connect of VLSI is presented. Current crowding in advanced metal systems may cause long term reliability problems for integrated circuits because the mean time to failure due to electromigration decreases as the maximum current density increases. The FCAP3 program (three-dimensional Poisson equation solving program) is used to study current flow in three-dimensional metal structures such as vias.

Methodology in Computer-Aided Design for Process and Device Development

The previous chapters have presented an overview of computer-aided design (CAD) in VLSI development, as well as the simulation tools currently used at Hewlett-Packard Laboratories. In this chapter, CAD is discussed from the user point of view. The methodology for using the simulation tools in the most effective way is presented. Then case studies will be presented in the following chapters which show in detail how simulation tools are used in device designs.

A Systematic Study of Transistor Design Traae-offs

The ability to manufacture circuits at, or near, fundamental density and speed limits is affected by the sensitivity of circuit parameters to variations in the manufacturing process, and by the ability to achieve tight control of the manufacturing process. Modifications of device or circuit design can alter the various dependencies, so that parts of the process that are intrinsically more controllable determine critical circuit properties. Critical dimensions determined by a series of steps (mask-making, exposure, develop, etch) are typically held to + /- 20%. Various ion implant doses and depths can be controlled to + /- 2% to 5%. For example, if there is an absolute minimum for channel length, then the circuit design must be set at L min +ΔL, where the yield of devices with L >L min is satisfactory and ΔL is a measure of the process variation with gate line width. L min must also allow for some overlap of the gate to source and drain. If the minimum channel length is set by a reliability factor, then the design target is determined by allowable early field failures rather than the allowable yield. This illustrates the difficulty in understanding the problems associated with scaling critical dimensions to less than 0.5 μm.