Jung-Suk Goo

A noise optimization technique for integrated low-noise amplifiers

Based on measured four-noise parameters and two-port noise theory, considerations for noise optimization of integrated low-noise amplifier (LNA) designs are presented. If arbitrary values of source impedance are allowed, optimal noise performance of the LNA is obtained by adjusting the source degeneration inductance. Even for a fixed source impedance, the integrated LNA can achieve near NF/sub min/ by choosing an appropriate device geometry along with an optimal bias condition. An 800 MHz LNA has been implemented in a standard 0.24 /spl mu/m CMOS technology. The amplifier possesses a 0.9 dB noise figure with a 7.1 dBm third-order input intercept point, while drawing 7.5 mW from a 2.0 V power supply, demonstrating that the proposed methodology can accurately predict noise performance of integrated LNA designs.

Transistors with dual work function metal gates by single full silicidation (FUSI) of polysilicon gates

Metal gate electrodes with two different work functions, /spl sim/4.5 and /spl sim/4.9 eV for NMOS and PMOS, respectively, were obtained by single-step full silicidation of poly gates. Reduction of polysilicon depletion was /spl sim/0.25 nm. Pile-up of arsenic at the NMOS dielectric is believed responsible for NiSi work function modification. Metal gate may offer little or no gate current reduction for the same T/sub oxinv/ as poly gate.

MOS C-V characterization of ultrathin gate oxide thickness (1.3-1.8 nm)

An equivalent circuit approach to MOS capacitance-voltage (C-V) modeling of ultrathin gate oxides (1.3-1.8 nm) is proposed. Capacitance simulation including polysilicon depletion is based on quantum mechanical (QM) corrections implemented in a two-dimensional (2-D) device simulator; tunneling current is calculated using a one-dimensional (1-D) Greens function solver. The sharp decrease in capacitance observed for gate oxides below 2.0 nm in both accumulation and inversion is modeled using distributed voltage-controlled RC networks. The imaginary components of small-signal input admittance obtained from AC network analysis agree well with measured capacitance.

An accurate and efficient high frequency noise simulation technique for deep submicron MOSFETs

Based on an active transmission line concept and two-dimensional (2-D) device simulations, an accurate and computationally efficient simulation technique for high frequency noise performance of MOSFETs is demonstrated. Using a Langevin stochastic source term model and small-signal equivalent circuit of the MOSFET, three intrinsic noise parameters (/spl gamma/, /spl delta/, and c) for the drain noise and induced gate noise are calculated. Validity and error analysis for the simulation are discussed by comparing the simulation results with theoretical results as well as measured data.

Scalability of strained-Si nMOSFETs down to 25 nm gate length

Strained-Si nMOSFETs with a standard polysilicon gate process were fabricated down to 25 nm gate length with well-behaved characteristics and small difference in short channel effects. The performance enhancement degrades linearly as the gate length becomes shorter, due to not only the parasitic resistance but also heavy halo implant. Thus the key integration issues are how to manage threshold difference and As diffusion without excess doping. With comparable doping and well controlled parasitic resistance, up to 45% improvement in drive current is predicted for sub-50 nm gate length strained-Si nMOSFETs on the Si/sub 0.8/Ge/sub 0.2/ substrate. In this work approximately 45% enhancement is in fact demonstrated for 35 nm gate length devices, through advanced channel engineering and implementation of metal gates.

Strained silicon NMOS with nickel-silicide metal gate

Strained Si NMOS transistors with Lgate down to 35 nm were fabricated using NiSi as a metal gate electrode material for the first time. Compared to poly gate devices, NiSi metal gate devices showed further enhanced performance with good control of short channel effects and no degradation in gate oxide integrity.

Direct tunneling current model for circuit simulation

This paper presents a compact direct tunneling current model for circuit simulation to predict ultra-thin gate oxide (<2.0 nm) CMOS circuit performance by introducing an explicit surface potential model with quantum-mechanical corrections. It demonstrates good agreement with the results from the numerical solver and measured data for the very-thin gate oxide thicknesses ranging 1.3-1.8 nm.

Band offset induced threshold variation in strained-Si nMOSFETs

Due to the offset in the valence band, strained-Si nMOSFETs exhibit a -100 mV threshold shift and 4% degradation of the subthreshold slope per each 10% increase of Ge content in the relaxed SiGe layer. The correlation between the threshold shift and strained layer thickness is investigated based on device simulations. In a certain range of the strained-Si layer thickness, the threshold and subthreshold slope change gradually, posing a concern of larger device parameter variation. A larger threshold distribution is observed in devices fabricated with a strained layer thickness comparable to the depletion depth.

Capacitance reconstruction from measured C-V in high leakage, nitride/oxide MOS

A reconstruction technique of the gate capacitance from anomalous capacitance-voltage (C-V) curves in high leakage dielectric MOSFETs is presented. An RC network is used to accommodate the distributed nature of MOSFETs and an optimization technique is applied to extract the intrinsic gate capacitance. Applicability of the method is demonstrated for ultra-thin nitride/oxide (N/O /spl sim/1.4 nm/0.7 nm) composite dielectric MOSFETs.

Physical origin of the excess thermal noise in short channel MOSFETs

The physical origin of the excess thermal noise in short channel MOSFETs is explained based on numerical noise simulation. The impedance field representation and extraction method demonstrate that the drain current noise is dominated by source side contributions. Analysis identifies local ac channel resistance variations as the primary controlling factor. The nonlocal nature of velocity results in a smaller derivative of the velocity with respect to the field which in turn causes a higher local ac resistance near the source junction.